CYP15G0101DXB
CYV15G0101DXB
Single-channel HOTLink II™ Transceiver
Single-channel HOTLink II™ Transceiver
Features
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Second-generation HOTLink
®
technology
Compliant to multiple standards
®
❐
ESCON , DVB-ASI, fibre channel and gigabit ethernet
(IEEE802.3z)
❐
CPRI™ compliant
❐
CYV15G0101DXB compliant to SMPTE 259M and SMPTE
292M
❐
8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to 1500 MBaud
serial data rate
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame™ Receive Framer
❐
Bit and byte alignment
❐
Comma or full K28.5 detect
❐
Single- or multi-byte framer for byte alignment
❐
Low-latency option
Synchronous LVTTL parallel input and parallel output interface
Internal phase-locked loops (PLLs) with no external PLL
components
Dual differential PECL-compatible serial inputs
❐
Internal DC-restoration
Dual differential PECL-compatible serial outputs
❐
Source matched for driving 50
Ω
transmission lines
❐
No external bias resistors required
❐
Signaling-rate controlled edge-rates
Optional elasticity buffer in receive path
Optional phase align buffer in transmit path
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Compatible with
❐
Fiber-optic modules
❐
Copper cables
❐
Circuit board traces
JTAG boundary scan
Built-in self-test (BIST) for at-speed link testing
Per-channel link quality indicator
❐
Analog signal detect
❐
Digital signal detect
Low power 1.25 W at 3.3 V typical
Single 3.3 V supply
100-ball BGA
Pb-free package option available
0.25 µ BiCMOS technology
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Functional Description
The CYP15G0101DXB
[1]
single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link (optical
fiber, balanced, and unbalanced copper transmission lines) at
signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an input
register, encodes each character for transport, and converts it to
serial data. The receive channel accepts serial data and converts
it to parallel data, frames the data to character boundaries,
decodes the framed characters into data and special characters,
and presents these characters to an output register.
Figure 1
illustrates typical connections between independent host
systems and corresponding CYP(V)15G0101DXB parts. As a
second-generation HOTLink device, the CYP(V)15G0101DXB
extends the HOTLink II family with enhanced levels of
integration and faster data rates, while maintaining serial-link
compatibility (data, command, and BIST) with other HOTLink
devices.
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Figure 1. HOTLink II System Connections
CYP(V)15G0101DXB
CYP(V)15G0101DXB
System Host
10
10
10
10
Serial Link
Backplane or Cabled
Connections
Note
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE
292M pathological test requirements. CYP(V)15G0101DXB refers both devices.
Cypress Semiconductor Corporation
Document Number: 38-02031 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 29, 2011
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System Host
CYP15G0101DXB
CYV15G0101DXB
The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE
292M compliance as per the EG34-1999 pathological test
requirements. The
transmit
(TX)
section
of
the
CYP(V)15G0101DXB single-channel HOTLink II consists of a
byte-wide channel. The channel can accept either eight-bit data
characters or pre-encoded 10-bit transmission characters. Data
characters are passed from the transmit input register to an
embedded 8B/10B encoder to improve their serial transmission
characteristics. These encoded characters are then serialized
and output from dual positive ECL (PECL)-compatible
differential transmission-line drivers at a bit-rate of either 10 or
20 times the input reference clock.
The receive (RX) section of the CYP(V)15G0101DXB
single-channel HOTLink II consists of a byte-wide channel. The
channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers and, using a
completely integrated PLL clock synchronizer, recovers the
timing information necessary for data reconstruction. The
recovered bit-stream is deserialized and framed into characters,
8B/10B decoded, and checked for transmission errors.
Recovered decoded characters are then written to an internal
elasticity buffer, and presented to the destination host system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The parallel I/O interface may be configured for numerous forms
of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path interfaces
from one or multiple sources, the receive interface may be
configured to present data relative to a recovered clock or to a
local reference clock.
The transmit and the receive channels contain BIST pattern
generators and checkers, respectively. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
both transmit and receive sections, as well as across the
interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, base-stations,
servers and video transmission systems.
The CYV15G0101DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed
by 1 one.
x10
Phase
Align
Buffer
Encoder
8B/10B
Elasticity
Buffer
Decoder
8B/10B
Framer
Serializer
Deserializer
TX
OUT1±
OUT2±
Document Number: 38-02031 Rev. *M
IN1±
IN2±
RXD[7:0]
RXST[2:0]
x11
TXD[7:0]
TXCT[1:0]
Transceiver Logic Block Diagram
RX
Page 2 of 44
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CYP15G0101DXB
CYV15G0101DXB
Logic Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
TXPER
Phase-Align
Buffer
Input
Register
12
12
12
BIST LFSR
8B/10B
SCSEL
TXD[7:0]
TXOP
TXCT[1:0]
TXCKSEL
TXCLK
TXRST
PARCTL
BOE[1:0]
BIST Enable
Latch
8
2
10
2
Character-Rate Clock
Character-Rate Clock
Transmit PLL
Clock Multiplier
Bit-Rate Clock
= Internal Signal
TRSTZ
Transmit
Mode
Shifter
Parity
Check
OUT1+
OUT1–
OUT2+
OUT2–
TXLB
H M L
4
Output
Enable
Latch
2
OELE
RXLE
RX PLL Enable
Latch
BISTLE
Character-Rate Clock
SDASEL
LPEN
INSEL
IN1+
IN1–
IN2+
IN2–
TXLB
FRAMCHAR
RFEN
RFMODE
DECMODE
RXRATE
RXMODE
RXCKSEL
JTAG
Boundary
Scan
Controller
TMS
TCLK
TDI
TDO
Receive
Signal
Monitor
Framer
Clock &
Data
Recovery
PLL
Shifter
LFI
Elasticity
Buffer
10B/8B
BIST
Output
Register
8
3
RXD[7:0]
RXOP
RXST[2:0]
Clock
Select
÷2
Delay
RXCLK+
RXCLK–
RXCLKC+
Document Number: 38-02031 Rev. *M
Page 3 of 44
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CYP15G0101DXB
CYV15G0101DXB
Contents
Pin Configuration ............................................................ 5
Pin Descriptions ............................................................... 6
CYP(V)15G0101DXB HOTLink II Operation .................. 12
CYP(V)15G0101DXB Transmit Data Path ................ 12
Transmit Modes ......................................................... 13
Transmit BIST ........................................................... 15
Serial Output Drivers ................................................. 16
Transmit PLL Clock Multiplier .................................... 16
CYP(V)15G0101DXB Receive Data Path ....................... 16
Serial Line Receivers ................................................ 16
Signal Detect/Link Fault ............................................ 17
Clock/Data Recovery ................................................. 18
Deserializer/Framer ................................................... 18
10B/8B Decoder Block .............................................. 19
Receive BIST Operation ............................................ 19
Receive Elasticity Buffer ............................................ 20
Receive Modes .......................................................... 20
Power Control ............................................................ 20
Output Bus ................................................................ 21
Parity Generation ...................................................... 22
JTAG Support ............................................................ 23
Maximum Ratings ........................................................... 25
Power-up Requirements ............................................ 25
DC Electrical Characteristics ........................................ 25
AC Test Loads and Waveforms ..................................... 26
CYP(V)15G0101DXB AC Characteristics ...................... 27
Switching Waveforms for the HOTLink II Transmitter 29
X3.230 Codes and Notation Conventions .................... 33
Notation Conventions ................................................ 33
8B/10B Transmission Code ....................................... 33
Transmission Order ................................................... 33
Valid and Invalid Transmission Characters ............... 33
Use of the Tables for Generating
Transmission Characters .......................................... 34
Use of the Tables for Checking the Validity
of Received Transmission Characters ...................... 34
Ordering Information ...................................................... 40
Ordering Code Definitions ......................................... 40
Package Diagram ............................................................ 41
Acronyms ........................................................................ 42
Document Conventions ................................................ 42
Document History Page ................................................. 43
Sales, Solutions, and Legal Information ...................... 44
Worldwide Sales and Design Support ....................... 44
Products .................................................................... 44
PSoC Solutions ......................................................... 44
Document Number: 38-02031 Rev. *M
Page 4 of 44
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CYP15G0101DXB
CYV15G0101DXB
Pin Configuration
Top View
1
A
B
C
D
E
F
G
H
J
K
V
CC
V
CC
RFEN
BOE[0]
BISTLE
RXST[2]
RXOP
RXD[0]
V
CC
V
CC
2
IN2+
IN2–
LPEN
BOE[1]
DECMODE
RXST[1]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
3
V
CC
TDO
RXLE
FRAMCHAR
OELE
RXST[0]
RXD[5]
RXD[6]
RXD[7]
V
CC
4
OUT2–
OUT2+
5
6
7
IN1+
IN1–
SPDSEL
GND
GND
GND
GND
TXD[3]
TXD[2]
TXD[1]
8
V
CC
#NC
[2]
PARCTL
TMS
TCLK
TXPER
TXOP
TXCLK
TXD[0]
V
CC
9
OUT1–
OUT1+
RFMODE
TRSTZ
10
V
CC
V
CC
INSEL
TDI
RXMODE TXMODE[1]
TXRATE TXMODE[0]
SDASEL
GND
GND
GND
GND
TXD[6]
TXD[5]
TXD[4]
RXCLKC+ RXRATE
GND
GND
GND
GND
LFI
RXCLK–
RXCLK+
GND
GND
GND
GND
TXCT[1]
TXCT[0]
TXD[7]
Bottom View
RXCKSEL TXCKSEL
REFCLK– REFCLK+
TXCLKO+ TXCLKO–
TXRST
#NC
[2]
SCSEL
#NC
[2]
V
CC
V
CC
10
V
CC
V
CC
INSEL
TDI
9
OUT1–
OUT1+
RFMODE
TRSTZ
8
V
CC
#NC
[2]
PARCTL
TMS
TCLK
TXPER
TXOP
TXCLK
TXD[0]
V
CC
7
IN1+
IN1–
SPDSEL
GND
GND
GND
GND
TXD[3]
TXD[2]
TXD[1]
6
5
4
OUT2–
OUT2+
3
V
CC
TDO
RXLE
FRAMCHAR
OELE
RXST[0]
RXD[5]
RXD[6]
RXD[7]
V
CC
2
IN2+
IN2–
LPEN
BOE[1]
DECMODE
RXST[1]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
1
V
CC
V
CC
RFEN
BOE[0]
BISTLE
RXST[2]
RXOP
RXD[0]
V
CC
V
CC
A
B
C
D
E
F
G
H
J
K
TXMODE[1] RXMODE
TXMODE[0] TXRATE
SDASEL
GND
GND
GND
GND
TXD[6]
TXD[5]
TXD[4]
RXRATE RXCLKC+
GND
GND
GND
GND
TXCT[1]
TXCT[0]
TXD[7]
GND
GND
GND
GND
LFI
RXCLK–
RXCLK+
TXCKSEL RXCKSEL
REFCLK+ REFCLK–
TXCLKO– TXCLKO+
#NC
[2]
V
CC
V
CC
TXRST
#NC
[2]
SCSEL
Note
2. #NC = Do Not Connect.
Document Number: 38-02031 Rev. *M
Page 5 of 44
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