CYDM064B16, CYDM128B16, CYDM256B16
1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL
®
Dual-Port Static RAM
Features
■
■
■
True dual-ported memory cells that allow simultaneous access
of the same memory location
4, 8, or 16K × 16 organization
Ultra Low operating power
❐
Active: ICC = 15 mA (typical) at 55 ns
❐
Standby: I
SB3
= 2
μA
(typical)
Small footprint: Available in a 6x6 mm 100-pin Pb-free vfBGA
Port independent 1.8V, 2.5V, and 3.0V IOs
Full asynchronous operation
Automatic power down
Pin select for Master or Slave
■
■
■
■
■
■
■
Expandable data bus to 32 bits with Master or Slave chip select
when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
Input read registers and output drive registers
INT flag for port-to-port communication
Separate upper-byte and lower-byte control
Industrial temperature ranges
■
■
■
■
■
Selection Guide for V
CC
= 1.8V
Parameter
Port IO Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
CYDM256B16, CYDM128B16, CYDM064B16
(-55)
1.8V -1.8V
55
15
2
2
Unit
V
ns
mA
μA
μA
Selection Guide for V
CC
= 2.5V
Parameter
Port IO Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
CYDM256B16, CYDM128B16, CYDM064B16
(-55)
2.5V-2.5V
55
28
6
4
Unit
V
ns
mA
μA
μA
Selection Guide for V
CC
= 3.0V
Parameter
Port IO Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
SB1
Typical Standby Current for I
SB3
CYDM256B16, CYDM128B16, CYDM064B16
(-55)
3.0V-3.0V
55
42
7
6
Unit
V
ns
mA
μA
μA
Cypress Semiconductor Corporation
Document #: 001-00217 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 31, 2008
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CYDM064B16, CYDM128B16, CYDM256B16
Functional Description
The CYDM256B16, CYDM128B16, and CYDM064B16 are low
power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration
schemes are included on the devices to handle situations when
multiple processors access the same piece of data. Two ports
are provided that permit independent, asynchronous access for
reads and writes to any location in memory. The devices can be
used as standalone 16-bit dual-port static RAMs or multiple
devices can be combined to function as a 32-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 32-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor or multi-
processor designs, communications status buffering, and
dual-port video or graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY indicates that the
port is trying to access the same location currently being
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems through a mail box.
The semaphores are used to pass a flag or token, from one port
to the other, to indicate that a shared resource is in use. The
semaphore logic consists of eight shared latches. Only one side
can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
The CYDM256B16, CYDM128B16, CYDM064B16 are available
in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
ACE
after CE or t
DOE
after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the
CYDM256B16) is the mailbox for the right port and the
second-highest memory location (FFE for the CYDM064B16,
1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program must be run and
the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy are
summarized in
Table 3
on page 7.
Busy
The CYDM256B16, CYDM128B16, and CYDM064B16 provide
on-chip arbitration to resolve simultaneous memory location
access (contention). If both port CEs are asserted and an
address match occurs within t
PS
of each other, the busy logic
determines which port has access. If t
PS
is violated, one port
definitely gains permission to the location. However, which port
gets this permission cannot be predicted. BUSY is asserted t
BLA
after an address match or t
BLC
after CE is taken LOW.
Power Supply
The core voltage (V
CC
) can be 1.8V, 2.5V, or 3.0V, as long as it
is lower than or equal to the IO voltage.
Each port can operate on independent IO voltages. This is
determined by what is connected to the V
DDIOL
and V
DDIOR
pins.
The supported IO standards are 1.8V or 2.5V LVCMOS and 3.0V
LVTTL.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see
Figure 5
on page 18) or the CE pin
(see
Figure 6
on page 18). Required inputs for noncontention
operations are summarized in
Table 2
on page 7.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output. Otherwise, the
data read is not deterministic. Data is valid on the port t
DDD
after
the data is presented on the other port.
Master/Slave
An M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This allows
the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (t
BLC
or t
BLA
). Otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, as a result, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
Document #: 001-00217 Rev. *F
Page 5 of 24
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