PRELIMINARY
CY8CNP102B, CY8CNP102E
N
onvolatile Programmable System-on-Chip
(
PSoC® NV)
Overview
The Cypress nonvolatile Programmable System-on-Chip
(PSoC
®
NV) processor combines a versatile Programmable
System-on-Chip™ (PSoC) core with an infinite endurance
nvSRAM in a single package. The PSoC NV combines an 8-bit
MCU core (M8C), configurable analog and digital functions, a
uniquely flexible IO interface, and a high density nvSRAM. This
creates versatile data logging solutions that provide value
through component integration and programmability. The flexible
core and a powerful development environment work to reduce
design complexity, component count, and development time.
■
Precision, Programmable Clocking
❐
Internal ±2.5% 24 and 48 MHz Oscillator
❐
24 and 48 MHz with optional 32.768 kHz Crystal
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
Flexible On-Chip Memory
❐
32K Bytes Flash Program Storage
❐
2K Bytes SRAM Data Storage
❐
256K Bytes secure store nvSRAM with data throughput be-
tween 100 KBPS and 1 MBPS
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Programmable Pin Configurations
❐
33 GPIOs
❐
25 mA Sink on all GPIO
❐
Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐
Up to 12 Analog Inputs on GPIOs
❐
Analog Outputs with 40 mA on 4 GPIOs
❐
Configurable Interrupt on all GPIOs
Additional System Resources
2
❐
I C Slave, Master, and MultiMaster to 100 Kbps
and 400 Kbps
❐
Watchdog and Sleep Timers
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full Featured, In Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
C Compilers, Assembler, and Linker
Temperature and Packaging
❐
Industrial Temperature Range: -40°C to +85°C
❐
Packaging: 100-pin TQFP
■
Features
■
Powerful Harvard Architecture Processor
❐
M8C processor speeds
• Up to 12 MHz for 3.3V operation
• Up to 24 MHz for 5V operation
❐
Two 8x8 multiply, 32 bit accumulate
❐
Low power at high speed
Operating Voltage
❐
3.3V (CY8CNP102B)
❐
5V (CY8CNP102E)
Advanced Peripherals
❐
12 Rail-to-Rail Analog PSoC blocks provide:
• Up to 14 bit ADCs
• Up to 9 bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• 8 Analog channels for simultaneous sampling
• Up to 820 SPS for each channel with 8 channel sampling
and logging
❐
16 Digital PSoC Blocks provide:
• 8 to 32 bit timers, counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full Duplex UARTs
• Multiple SPI™ Masters and Slaves
❐
Complex Peripherals by Combining Blocks
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document #: 001-43991 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 20, 2008
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Logic Block Diagram
Document #: 001-43991 Rev. *D
Page 2 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Pinouts
Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm)
Table 1. Pin Definitions - 100-Pin TQFP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin Name
P0_5
P0_3
P0_1
P2_7
P2_5
P2_3
P2_1
Vcc
DNU
DNU
DNU
DNU
DNU
NC
P3_5
EN_W
P3_1
IO
IO
Type
Digital
IO
IO
IO
IO
IO
IO
IO
Power
I
I
Analog
IO
IO
I
Pin Definition
Analog Column Mux Input and Column Output
Analog Column Mux Input and Column Output
Analog Column Mux Input, GPIO
GPIO
GPIO
Direct Switched Capacitor Block Input
Direct Switched Capacitor Block Input
Supply Voltage
Reserved for test modes - Do Not Use
Reserved for test modes - Do Not Use
Reserved for test modes - Do Not Use
Reserved for test modes - Do Not Use
Reserved for test modes - Do Not Use
Not connected on the die
GPIO
Connect to Pin 26 (EN_W to NV_W)
GPIO
Document #: 001-43991 Rev. *D
Page 3 of 38
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 1. Pin Definitions - 100-Pin TQFP
(continued)
Pin Number
18
19
20
21
22
23
24
25
26
27 - 34
35 - 39
40 - 47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72-73
74
75
76
77
78
Pin Name
P5_7
P5_5
P5_3
P5_1
P1_7
P1_5
P1_3
P1_1
NV_W
NC
Vss
NC
DNU
NV_A1
NV_A2
P1_0
P1_2
P1_6
P5_0
P5_2
P5_4
P5_6
EN_A1
EN_A2
EN_O
EN_C
XRES
VCAP
Vcc
P2_0
P2_2
P2_4
P2_6
P0_0
P0_2
P0_4
NC
P0_6
Vcc
NV_O
DNU
NC
IO
Power
I
IO
IO
IO
IO
IO
IO
IO
I
IO
IO
Input
Power
Power
I
I
IO
IO
IO
IO
IO
IO
IO
Power
Type
Digital
IO
IO
IO
IO
IO
IO
IO
IO
Analog
GPIO
GPIO
GPIO
GPIO
I2C Serial Clock (SCL), GPIO
I2C Serial Data (SDA), GPIO
GPIO
Serial Clock (SCL), Crystal (XTALin), GPIO
Connect to pin 16 (NV_W to EN_W)
Not connected on the die
Ground
Not connected on the die
Reserved for test modes - Do Not Use
Connect to pin 58 (NV_A1 to EN_A1)
Connect to pin 59 (NV_A2 to EN_A2)
Serial Data (SDA), Crystal (XTALout), GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Connect to Pin 49 (EN_A1 to NV_A1)
Connect to Pin 50 (EN_A2 to NV_A2)
Connect to Pin 76 (EN_O to NV_O)
Connect to Pin 99 (EN_C to NV_C)
Active high external reset (Internal Pull down)
External Capacitor connection for nvSRAM
Supply Voltage
Direct Switched Capacitor Block Input, GPIO
Direct Switched Capacitor Block Input, GPIO
External Analog GND, GPIO
External Voltage Ref, GPIO
Analog Column Mux Input, GPIO
Analog Column Mux Input and Column Output
Analog Column Mux Input and Column Output
Not connected on the die
Analog Column Mux Input, GPIO
Supply Voltage
Connect to Pin 60 (NV_O to EN_O)
Reserved for test modes - Do Not Use
Not connected on the die
Page 4 of 38
Pin Definition
Document #: 001-43991 Rev. *D
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Table 1. Pin Definitions - 100-Pin TQFP
(continued)
Pin Number
79
80
81 - 85
86 - 90
91 - 98
99
100
Pin Name
HSB#
Vcc
NC
Vss
NC
NV_C
P0_7
IO
I
Power
Power
Type
Digital
Analog
Supply Voltage
Not connected on the die
Ground
Not connected on the die
Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.
Analog Column Mux Input, GPIO
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Pin Definition
Weak Pull up. Connect 10kΩ to Vcc.
PSoC NV Functional Overview
The PSoC NV provides a versatile microcontroller core (M8C),
Flash program memory, nvSRAM data memory, and
configurable analog and digital peripheral blocks in a single
package. The flexible digital and analog IOs and routing matrix
create a powerful embedded and flexible mixed signal
System-on-Chip (SoC).
The device incorporates configurable analog and digital blocks,
interconnect circuitry around an MCU subsystem, and an infinite
endurance nvSRAM. This enables high level integration in
consumer, industrial, and automotive applications, where
preventing data loss under all conditions is vital.
nvSRAM Data Memory
The nvSRAM memory block is byte addressable fast static RAM
with a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
®
technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, when independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down, and
data is restored to the SRAM (the RECALL operation) from the
nonvolatile memory on power up. All cells store and recall data
in parallel.
Both the STORE and RECALL operations may be initiated under
software control. The PSoC NV user module embedded in the
PSoC Designer Tool provides all necessary APIs to initiate
software STORE and RECALL function from the user program.
PSoC NV Core
The PSoC NV core is a powerful PSoC engine that supports a
rich feature set. The core includes a M8C CPU, memory, clocks,
and configurable GPIO (General Purpose IO). The M8C CPU
core is a powerful processor with speeds up to 24 MHz, providing
a four MIPS 8-bit Harvard architecture microprocessor. The CPU
uses an interrupt controller with 25 vectors, to simplify
programming of real time embedded events. Program execution
is timed and protected using the included Sleep and Watch Dog
Timers (WDT).
On-chip memory encompasses 32 KB Flash for program
storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data
logging, and up to 2 KB EEPROM emulated using Flash.
Program Flash uses four protection levels on blocks of 64 bytes,
allowing customized software IP protection. The nvSRAM
combines a static RAM cell and a SONOS cell to provide an
infinite endurance nonvolatile memory block. The memory is
random access and is accessed using a user module provided
with the device.
The device incorporates flexible internal clock generators,
including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz Internal Low speed Oscillator (ILO) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC NV
device.
GPIOs provide connection to the CPU, and digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
Document #: 001-43991 Rev. *D
nvSRAM Operation
The nvSRAM is made up of an SRAM memory cell, and a
nonvolatile QuantumTrap cell paired in the same physical cell.
The SRAM memory cell operates as a standard fast static, and
all READ and WRITE takes place from the SRAM during normal
operation.
During the STORE and RECALL operations, SRAM READ and
WRITE operations are inhibited, and internal operations transfer
data between the SRAM and nonvolatile cells. The nvSRAM
provides infinite RECALL operations from the nonvolatile cells
and up to 200,000 STORE operations.
To reduce unnecessary nonvolatile stores, AutoStore
®
is ignored
unless at least one WRITE operation is complete after the most
recent STORE or RECALL cycle. Software initiated STORE
cycles are performed regardless of whether a WRITE operation
has taken place. Embedded APIs provide a seamless interface
to the nvSRAM.
During normal operation, the embedded nvSRAM draws current
from Vcc to charge a capacitor connected to the V
CAP
pin. This
stored charge is used by the chip to perform a STORE operation.
If the voltage on the Vcc pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from Vcc and STORE
operation is initiated.
Page 5 of 38
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