CY8C29466, CY8C29566
CY8C29666, CY8C29866
PSoC
®
Programmable System-on-Chip™
PSoC
®
Programmable System-on-Chip
Features
■
Powerful Harvard-architecture processor
❐
M8C processor speeds to 24 MHz
❐
Two 8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
Operating voltage: 3.0 V to 5.25 V
❐
Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐
Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
blocks)
❐
12 rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐
16 digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse-width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Up to four full-duplex universal asynchronous receiver
transmitters (UARTs)
• Multiple serial peripheral interface (SPI) masters or slaves
• Can connect to all general-purpose I/O (GPIO) pins
❐
Create complex peripherals by combining blocks
Precision, programmable clocking
❐
Internal ±2.5% 24- / 48-MHz main oscillator
❐
24- / 48-MHz with optional 32.768 kHz crystal
❐
Optional external oscillator, up to 24 MHz
❐
Internal oscillator for watchdog and sleep
Flexible on-chip memory
❐
32 KB flash program storage 50,000 erase/write cycles
❐
2 KB static random access memory (SRAM) data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
Programmable pin configurations
❐
25-mA sink, 10-mA source on all GPIOs
❐
Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
❐
Eight standard analog inputs on GPIOs, plus four additional
analog inputs with restricted routing
❐
Four 40 mA analog outputs on GPIOs
❐
Configurable interrupt on all GPIOs
■
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low-voltage detection (LVD)
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full-featured in-circuit emulator (ICE) and
programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
❐
Complex events
❐
C compilers, assembler, and linker
■
■
Logic Block Diagram
Port
7
Port
6
Port
5
Port
4
Port
3
Port
2
Port
1
Port 0 with
Analog Drivers
PSoC
CORE
System Bus
■
Global Digital Interconnect
SRAM
2 KB
Interrupt
Controller
Global Analog Interconnect
Flash 32KB
Sleep and
Watchdog
SROM
CPU Core (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
■
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
POR and LVD
Decimator
I
2
C
System Resets
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12013 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 7, 2011
[+] Feedback
CY8C29466, CY8C29566
CY8C29666, CY8C29866
Contents
PSoC Programmable System-on-Chip ........................... 1
Features ............................................................................. 1
Logic Block Diagram ........................................................ 1
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
28-Pin Part Pinout ....................................................... 8
44-Pin Part Pinout ....................................................... 9
48-Pin Part Pinout ..................................................... 10
100-Pin Part Pinout ................................................... 12
100-Pin Part Pinout (On-Chip Debug) ....................... 14
Register Reference ......................................................... 16
Register Conventions ................................................ 16
Register Mapping Tables .......................................... 16
Electrical Specifications ................................................ 19
Absolute Maximum Ratings ....................................... 19
Operating Temperature ............................................ 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 35
Packaging Information ................................................... 44
Packaging Dimensions .............................................. 44
Thermal Impedances ................................................ 49
Capacitance on Crystal Pins .................................... 49
Solder Reflow Specifications ..................................... 49
Development Tool Selection ......................................... 50
Software .................................................................... 50
Development Kits ...................................................... 50
Evaluation Tools ........................................................ 50
Device Programmers ................................................. 51
Accessories (Emulation and Programming) ................ 51
Ordering Information ...................................................... 52
Ordering Code Definitions ......................................... 52
Acronyms ........................................................................ 53
Acronyms Used ......................................................... 53
Reference Documents .................................................... 53
Document Conventions ............................................. 54
Units of Measure ....................................................... 54
Numeric Conventions ................................................ 54
Glossary .......................................................................... 54
Document History Page ................................................ 59
Sales, Solutions, and Legal Information ...................... 61
Worldwide Sales and Design Support ....................... 61
Products .................................................................... 61
PSoC Solutions ......................................................... 61
Document Number: 38-12013 Rev. *S
Page 2 of 61
[+] Feedback
CY8C29466, CY8C29566
CY8C29666, CY8C29866
PSoC Functional Overview
The PSoC family consists of many Programmable
System-on-Chip controller devices. These devices are designed
to replace multiple traditional microcontroller unit (MCU)-based
system components with one, low-cost single-chip program-
mable device. PSoC devices include configurable blocks of
analog and digital logic, as well as programmable interconnects.
This architecture allows you to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast central processing unit (CPU),
flash program memory, SRAM data memory, and configurable
I/O are included in a range of convenient pinouts and packages.
The PSoC architecture, as illustrated in the
Logic Block Diagram
on page 1,
consists of four main areas: PSoC core, digital
system, analog system, and system resources. Configurable
global busing allows all of the device resources to be combined
into a complete custom system. The PSoC CY8C29x66 family
can have up to five I/O ports that connect to the global digital and
analog interconnects, providing access to 8 digital blocks and
12 analog blocks.
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
Digital System
The digital system is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user modules.
Figure 1. Digital System Block Diagram
Port7
Port6
Port5
Port4
Port3
Port2
Port1
Port0
Digital Clocks
From Core
To System Bus
To Analog
System
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIOs.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a 4 million instructions per second (MIPS)
8-bit Harvard-architecture microprocessor. The CPU uses an
interrupt controller with 17 vectors, to simplify programming of
real-time embedded events. Program execution is timed and
protected using the included sleep and watchdog timers (WDT).
Memory uses 16 KB of flash for program storage, 256 bytes of
SRAM for data storage, and up to 2 KB of EEPROM emulated
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software information
protection (IP).
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low-power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the
32.768 kHz external crystal oscillator (ECO) is available for use
as a real-time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, and digital and
analog resources of the device. Each pin’s drive mode may be
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row0
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Configuration
8
8
Row Input
Configuration
8
Row1
DBB10
DBB11
DCB12
4
DCB13
4
8
Row Output
Configuration
Row Input
Configuration
Row2
DBB20
DBB21
DCB22
4
DCB23
4
Row Output
Configuration
Row Input
Configuration
Row3
DBB30
DBB31
DCB32
4
DCB33
4
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12013 Rev. *S
Page 3 of 61
[+] Feedback
CY8C29466, CY8C29566
CY8C29666, CY8C29866
Digital peripheral configurations include:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
DTMF Dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
PWMs (8- to 32-bit)
PWMs with dead band (8- to 32-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8-bit with selectable parity (up to 2)
SPI slave and master (up to 2)
I
2
C slave and multi-master (one available as a system
resource)
CRC generator (8- to 32-bit)
IrDA (up to 2)
PRS generators (8- to 32-bit)
Analog blocks are provided in columns of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in
Figure 2.
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled
“PSoC Device
Characteristics”
on page 5.
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
Analog System
The analog system is composed of 12 configurable blocks, each
containing an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
■
■
■
■
■
■
■
■
■
ACI0[1:0]
Array Input Configuration
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
ACB02
ASC12
ASD22
ACB03
ASD13
ASC23
ADCs (up to 4, with 6- to 14-bit resolution; selectable as
incremental, delta sigma, and SAR)
Filters (2-, 4-, 6-, and 8-pole band pass, low pass, and notch)
Amplifiers (up to 4, with selectable gain to 48x)
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
Comparators (up to 4, with 16 selectable thresholds)
DACs (up to 4, with 6-bit to 9-bit resolution)
Multiplying DACs (up to 4, with 6-bit to 9-bit resolution)
High current output drivers (four with 30-mA drive as a core
resource)
1.3-V reference (as a system resource)
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12013 Rev. *S
Page 4 of 61
[+] Feedback
CY8C29466, CY8C29566
CY8C29666, CY8C29866
Additional System Resources
System resources, some of which were previously listed, provide
additional capability useful to complete systems. Additional
resources include a multiplier, decimator, switch mode pump,
low-voltage detection, and power-on-reset (POR).
■
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Multiply accumulate (MAC) provides a fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of delta
sigma ADCs.
The I
2
C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■
An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
An integrated switch-mode pump (SMP) generates normal
operating voltages from a single 1.2 V battery cell, providing a
low cost boost converter.
■
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this
datasheet is highlighted.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C28xxx
CY8C27x43
CY8C24x94
CY8C24x23A
CY8C23x33
CY8C22x45
CY8C21x45
CY8C21x34
CY8C21x23
CY8C20x34
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[1]
12
6
6
4
6
[1]
6
4
[1]
[1]
SRAM
Size
2K
1K
256
1K
256
256
1K
512
512
256
512
up to 2 K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
16 K
8K
8K
4K
8K
up to 32 K
4
[1]
3
[1,2]
3
[1,2]
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense
®
.
Document Number: 38-12013 Rev. *S
Page 5 of 61
[+] Feedback
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
