CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
®
PSoC Mixed-Signal Array
Features
■
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Low power at high speed
❐
2.4V to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.0V using On-Chip Switch
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
Advanced Peripherals (PSoC Blocks)
❐
4 Analog Type “E” PSoC Blocks provide:
• 2 Comparators with DAC Refs
• Single or Dual 8-Bit 28 Channel ADC
❐
4 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART, SPI™ Master or Slave
• Connectable to All GPIO Pins
❐
Complex Peripherals by Combining Blocks
Flexible On-Chip Memory
❐
8K Flash Program Storage 50,000 Erase/Write Cycles
❐
512 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP™)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
Complete Development Tools
❐
Free Development Software
(PSoC Designer™)
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
Programmable Pin Configurations
❐
25 mA Drive on All GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to 8 Analog Inputs on GPIO
❐
Configurable Interrupt on All GPIO
Versatile Analog Mux
❐
Common Internal Analog Bus
❐
Simultaneous Connection of IO Combinations
❐
Capacitive Sensing Application Capability
Additional System Resources
2
❐
I C™ Master, Slave and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
■
Block Diagram
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 38-12025 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 18, 2008
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CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
PSoC
®
Functional Overview
The PSoC® family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one low cost single-chip programmable component. A PSoC
device includes configurable blocks of analog and digital logic,
and programmable interconnect. This architecture enables the
user to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, shown in
Figure 1,
consists of four main
areas: the Core, the System Resources, the Digital System, and
the Analog System. Configurable global bus resources allow
combining all the device resources into a complete custom
system. Each CY8C21x34 PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 general purpose IO (GPIO) are also included.
The GPIO provide access to the global digital and analog inter-
connects.
The Digital System
The Digital System consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references. Digital peripheral configurations include
the following.
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32 bit)
PWMs with Dead band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity
SPI master and slave
I2C slave and multi-master
Cyclical Redundancy Checker/Generator (8 to 32 bit)
IrDA
Pseudo Random Sequence Generators (8 to 32 bit)
The PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor.
System Resources provide the following additional capabilities:
■
■
■
■
■
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 1
on page 4.
Figure 1. Digital System Block Diagram
Port 3
Port 1
Port 2
Port 0
Digital clocks to increase the flexibility of the PSoC
mixed-signal arrays.
I2C functionality to implement an I2C master and slave.
An internal voltage reference, MultiMaster, that provides an
absolute value of 1.3V to a number of PSoC subsystems.
A switch mode pump (SMP) that generates normal operating
voltages off a single battery cell.
Various system resets supported by the M8C.
Digital Clocks
FromCore
To System Bus
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
DBB00
DBB01
DCB02
Row Input
Configuration
The Digital System consists of an array of digital PSoC blocks
that may be configured into any number of digital peripherals.
The digital blocks are connected to the GPIO through a series of
global buses that can route any signal to any pin, freeing designs
from the constraints of a fixed peripheral controller.
The Analog System consists of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion up to 8
bits in precision.
8
8
4
DCB03
4
Row Output
Configuration
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 38-12025 Rev. *M
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The Analog System
The Analog System consists of 4 configurable blocks that allow
the creation of complex analog signal flows. Analog peripherals
are very flexible and may be customized to support specific
application requirements. Some of the common PSoC analog
functions for this device (most available as user modules) are:
■
■
■
■
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins may
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8:1
analog input multiplexer provides a second path to bring Port 0
pins to the analog array.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Analog-to-digital converters (single or dual, with 8-bit
resolution)
Pin-to-pin comparator
Single-ended comparators (up to 2) with absolute (1.3V)
reference or 8-bit DAC reference
1.3V reference (as a System Resource)
Track pad, finger sensing.
Chip-wide mux that allows analog input from any IO pin.
Crosspoint connection between any IO pin combinations.
In most PSoC devices, analog blocks are provided in columns of
three, which includes one CT (Continuous Time) and two SC
(Switched Capacitor) blocks. The CY8C21x34 devices provide
limited functionality Type “E” analog blocks. Each column
contains one CT Type E block and one SC Type E block. Refer
to the
PSoC Mixed-Signal Array Technical Reference Manual
for
detailed information on the CY8C21x34’s Type E analog blocks.
Figure 2. Analog System Block Diagram
When designing capacitive sensing applications, refer to the
signal-to-noise system level requirement found in Application
Note
AN2403
on
the
Cypress
web
site
at
http://www.cypress.com.
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch mode pump, low
voltage detection, and power on reset. Brief statements
describing the merits of each system resource follow.
■
Array Input
Configuration
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
Versatile analog multiplexer system.
■
ACI0[1:0]
A IO
ll
X
X
X
X
ACI1[1:0]
■
ACOL1MUX
Analog MuxBus
■
X
Array
ACE00
ASE10
ACE01
ASE11
■
■
Document Number: 38-12025 Rev. *M
Page 3 of 43
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks.
Table 1
lists the resources available for specific
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Table 1. PSoC Device Characteristics
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Digital
IO
PSoC Part
Number
CY8C29x66
CY8C27x43
CY8C24x94
Flash
Size
32K
16K
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com,
click the Online Store shopping cart
icon at the bottom of the web page, and click
PSoC (Program-
mable System-on-Chip)
to view a current list of available items.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced
analog
and
CapSense.
Go
to
http://www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
http://www.cypress.com,
click on Design
Support located on the left side of the web page, and select
CYPros Consultants.
up to 4
64
up to 2
44
56
1
16
8
4
4
4
4
0
12
12
48
12
28
8
28
4
4
2
2
0
0
0
4
4
2
2
2
2
0
12
12
6
6
4
a
4
a
3
b
2K
256 16K
Bytes
1K
256 4K
Bytes
512 8K
Bytes
256 4K
Bytes
512 8K
Bytes
CY8C24x23A up to 1
24
CY8C21x34
CY8C21x23
CY8C20x34
up to 1
28
16
1
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
response at
http://www.cypress.com/support.
Application Notes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com
web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are sorted by date by default.
up to 0
28
a.
Limited analog functionality
.
b. Two analog blocks and one CapSense.
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information with
detailed programming information, refer the
PSoC Mixed-Signal
Array
Technical
Reference
Manual
available
at
http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets at
http://www.cypress.com.
Development Tools
PSoC Designer is a Microsoft
®
Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
Millennium (Me), or Windows XP. (See
Figure 3
on page 5)
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
Document Number: 38-12025 Rev. *M
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CY8C21434, CY8C21334, CY8C21234
Figure 3. PSoC Designer Subsystems
Design Browser
The Design Browser enables users to select and import
preconfigured designs into the user’s project. Users can easily
browse a catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler.
The macro assembler allows the seamless
merging of the assembly code with C code. The link libraries
automatically use absolute addressing or are compiled in relative
mode, and linked with other software modules to get absolute
addressing.
C Language Compiler.
A C language compiler that supports
the PSoC family of devices is available. Even if you have never
worked in the C language before, the product quickly helps you
create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem enables the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration allows changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24 MHz) operation.
Document Number: 38-12025 Rev. *M
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