CY8C21345
CY8C22345, CY8C22545
PSoC
®
Programmable System-on-Chip
Features
■
■
Powerful Harvard-architecture processor:
❐
M8C processor speeds up to 24 MHz
❐
8 × 8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
3.0 V to 5.25 V operating voltage
❐
Industrial temperature range: -40°C to +85°C
Advanced peripherals (PSoC
®
Blocks)
❐
Six analog type “E” PSoC blocks provide:
• Single or dual 8-Bit ADC
• Comparators (up to four)
❐
Up to eight digital PSoC blocks provide:
• 8 to 32-Bit Timers, counters, and PWMs
• One shot, multi shot mode support in timers and PWMs
• PWM with deadband support in one digital block
• Shift register, CRC, and PRS modules
• Full duplex UART
• Multiple SPI masters or slaves, variable data length
Support: 8- to 16-Bit
• Can be connected to all GPIO pins
❐
Complex peripherals by combining blocks
❐
Shift function support for FSK detection
❐
Powerful synchronize feature support. Analog module
operations can be synchronized by digital blocks or external
signals.
High speed 10-bit SAR ADC
with sample and hold optimized for
embedded control
Programmable pin configurations:
❐
25 mA sink, 10 mA source on all GPIOs
❐
Pull-up, pull-down, high Z, Strong, or open-drain drive modes
on all GPIOs
❐
Up to 38 analog inputs on GPIOs
❐
Configurable interrupt on all GPIOs
Additional system resources:
2
❐
I C™ slave, master, and multimaster to 400 kHz
❐
Supports hardware addressing feature
❐
Watchdog and sleep timers
❐
User configurable low voltage detection
❐
Integrated supervisory circuit
❐
On-Chip precision voltage reference
❐
Supports RTC block into digital peripheral logic
■
■
Top Level Block Diagram
Port 4
Port 3
Port 2 Port 1 Port 0
Analog
Drivers
PSoC Core
Global Digital Interconnect
SRAM
1K
Interrupt
Controller
SROM
Global Analog Interconnect
Flash 16K
Sleep and
Watchdog
■
■
CPU Core (M8C)
Precision, programmable clocking:
❐
Internal ± 5% 24/48 MHz oscillator across the industrial
temperature range
❐
High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐
Optional external oscillator, up to 24 MHz
❐
Internal/external oscillator for watchdog and sleep
Flexible on-chip memory:
❐
Up to 16 KB flash program storage 50,000 erase/write cycles
❐
Up to 1-KB SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Optimized CapSense
®
resource:
❐
Two IDAC support up to 640 µA source current to replace
external resistor
❐
Two dedicated clock resources for CapSense:
• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
❐
Dedicated 16-bit timers/counters for capsense scanning
❐
Support dual CSD channels simultaneous scanning
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block Array
DBC DBC DCC DCC
ANALOG SYSTEM
Analog Input
Muxing(L,R)
Analog
Ref
■
=
ROW 1
DBC DBC DCC DCC
Analog Block Array
CTE
SCE
CTE
SCE
CTE
CTE
ROW 2
System Bus
CapSense
Digital Resource
■
10-bit SAR
ADC
Digital
Clocks
MACs
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-43084 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 23, 2011
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CY8C21345
CY8C22345, CY8C22545
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
CY8C22345, CY8C21345 28-Pin SOIC ...................... 8
CY8C22545 44-Pin TQFP ........................................... 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 14
Operating Temperature ............................................ 14
DC Electrical Characteristics ..................................... 15
AC Electrical Characteristics ..................................... 19
Packaging Information ................................................... 25
Thermal Impedances ................................................ 26
Solder Reflow Specifications ..................................... 26
Ordering Information ...................................................... 26
Ordering Code Definitions ........................................ 26
Acronyms ........................................................................ 27
Acronyms Used ......................................................... 27
Reference Documents .................................................... 27
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Numeric Conventions ................................................ 28
Glossary .......................................................................... 28
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Document Number: 001-43084 Rev. *M
Page 2 of 34
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CY8C22345, CY8C22545
PSoC Functional Overview
The PSoC family consists of many On-Chip Controller devices.
These devices are designed to replace multiple traditional
MCU-based system components with one low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, and programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, shown in
Figure 1,
consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. Configurable global busing allows the combining of
all the device resources into a complete custom system. The
PSoC family can have up to five I/O ports connecting to the
global digital and analog interconnects, providing access to eight
digital blocks and six analog blocks.
Digital System
The Digital System is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 4
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
8
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with 21 vectors,
to simplify the programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16 KB of Flash for program storage, 1K
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator). The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz ILO (internal low speed oscillator) is
provided for the Sleep timer and WDT. If crystal accuracy is
required, the ECO (32.768 kHz external crystal oscillator) is
available for use as a Real Time Clock (RTC), and can optionally
generate a crystal-accurate 24 MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
System Resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
8
8
Row Input
Configuration
8
Row 1
DBC00
DBC01
DCC02
DCC03
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
■
■
■
■
■
■
■
■
■
■
PWMs (8 to 32-Bit)
PWMs with Dead band (8 to 32-Bit)
Counters (8 to 32-Bit)
Timers (8 to 32-Bit)
UART 8 Bit with Selectable Parity (Up to Two)
SPI Master and Slave (Up to Two)
Shift Register (1 to 32-Bit)
I2C Slave and Master (One Available as a System Resource)
Cyclical Redundancy Checker/Generator (8 to 32-Bit)
IrDA (Up to Two)
Pseudo Random Sequence Generators (8 to 32-Bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides a choice of
system resources for your application. Family resources are
shown in
Table 1
on page 5.
Document Number: 001-43084 Rev. *M
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CY8C22345, CY8C22545
Analog System
The Analog System consists of a 10-bit SAR ADC and six
configurable blocks.
The programmable 10-bit SAR ADC is an optimized ADC that
can be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL
(true for V
DD
≥
3.0 V and Vref
≥
3.0 V). External filters are
required on ADC input channels for antialiasing. This ensures
that any out-of-band content is not folded into the input signal
band.
Reconfigurable analog resources allow creating complex analog
signal flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common PSoC analog functions (most available as
user modules) are:
■
■
■
■
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a MAC, low voltage
detection, and power on reset. The merits of each system
resource are:
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Additional Digital resources and clocks optimized for CSD.
Support “RTC” block into digital peripheral logic.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
■
■
Analog-to-Digital converters (Single or Dual, with 8-bit
resolution)
Pin-to-pin Comparator
Single ended comparators with absolute (1.3 V) reference or
5-bit DAC reference
1.3 V reference (as a System Resource)
■
■
Analog blocks are provided in columns of four, which include
CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks.
These devices provide limited functionality Type “E” analog
blocks.
Figure 2. Analog System Block Diagram
Array Input Configuration
■
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
ACE00
ASE10
ACE01
ASE11
ACE10
ACE11
Block Array
AmuxL
AmuxR
P0[0:7]
ACI2[3:0]
10 bit SAR ADC
Analog Reference
Interface to
Digital System
Reference
Generators
AGND
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-43084 Rev. *M
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CY8C22345, CY8C22545
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. The following table lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
[1]
CY8C28xxx
CY8C27x43
CY8C24x94
[1]
CY8C24x23A
[1]
CY8C23x33
CY8C22x45
[1]
CY8C21x45
[1]
CY8C21x34
[1]
CY8C21x23
CY8C20x34
[1]
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[2]
12
6
6
4
6
[2]
6
[2]
4
[2]
4
[2]
3
[2,3]
3
[2,3]
SRAM
Size
2K
1K
256
1K
256
256
1K
512
512
256
512
up to 2 K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
16 K
8K
8K
4K
8K
up to 32 K
Getting Started
For in-depth information, along with detailed programming
details, see the
PSoC
®
Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest
PSoC device datasheets
on the web.
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the
CYPros Consultants
web site.
Application Notes
Cypress application notes
are an excellent introduction to the
wide variety of possible PSoC designs.
Solutions Library
Visit our growing
library of solution focused designs.
Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Development Kits
PSoC Development Kits
are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Technical Support
Technical support
– including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Training
Free PSoC technical training
(on demand, webinars, and
workshops), which is available online via
www.cypress.com,
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
3. Two analog blocks and one CapSense
®
block.
Document Number: 001-43084 Rev. *M
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