CY7C67200
EZ-OTG™ Programmable USB
On-The-Go
EZ-OTG Features
• Single-chip programmable USB dual-role (Host/Peripheral)
controller with two configurable Serial Interface Engines
(SIEs) and two USB ports
• Supports USB OTG protocol
• On-chip 48-MHz 16-bit processor with dynamically
switchable clock speed
• Configurable IO block supports a variety of IO options or up
to 25 bits of General Purpose IO (GPIO)
• 4K × 16 internal mask ROM contains built-in BIOS that
supports a communication-ready state with access to I
2
C™
EEPROM interface, external ROM, UART, or USB
• 8K x 16 internal RAM for code and data buffering
• 16-bit parallel host port interface (HPI) with DMA/Mailbox
data path for an external processor to directly access all
on-chip memory and control on-chip SIEs
• Fast serial port supports from 9600 baud to 2.0M baud
•
•
•
•
SPI supports both master and slave
Supports 12 MHz external crystal or clock
2.7V to 3.6V power supply voltage
Package option: 48-pin FBGA
Typical Applications
EZ-OTG is a very powerful and flexible dual-role USB
controller that supports a wide variety of applications. It is
primarily intended to enable USB OTG capability in applica-
tions such as:
• Cellular phones
• PDAs and pocket PCs
• Video and digital still cameras
• MP3 players
• Mass storage devices
Block Diagram
CY7C67200
CY7C67200
Control
Timer 0
Timer 1
nRESET
Watchdog
UART I/F
Vbus, ID
OTG
D+,D-
USB-A
I2C
EEPROM I/F
HOST/
Peripheral
USB Ports
SIE1
HSS I/F
SHARED INPUT/OUTPUT PINS
CY16
16-bit RISC CORE
GPIO [24:0]
SPI I/F
D+,D-
USB-A
SIE2
4Kx16
ROM BIOS
8Kx16
RAM
HPI I/F
X1
X2
PLL
Mobile
Power
Booster
GPIO
Cypress Semiconductor Corporation
Document #: 38-08014 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 14, 2006
[+] Feedback
CY7C67200
Introduction
EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first
USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is
designed to easily interface to most high-performance CPUs
to add USB host functionality. EZ-OTG has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-OTG also has a programmable IO interface block
allowing a wide range of interface options.
Interrupts
EZ-OTG provides 128 interrupt vectors. The first 48 vectors
are hardware interrupts and the following 80 vectors are
software interrupts.
General Timers and Watchdog Timer
EZ-OTG has two built-in programmable timers and a
watchdog timer. All three timers can generate an interrupt to
the EZ-OTG.
Power Management
EZ-OTG has one main power-saving mode, Sleep. Sleep
mode pauses all operations and provides the lowest power
state.
Processor Core Functional Overview
An overview of the processor core components are presented
in this section.
Processor
EZ-OTG has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-OTG requires a 12 MHz source for clocking. Either an
external crystal or TTL-level oscillator may be used. EZ-OTG
has an internal PLL that produces a 48 MHz internal clock from
the 12 MHz source.
Memory
EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-OTG BIOS.
The internal RAM can be used for program code or data.
Table 1. Interface Options for GPIO Pins
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
HPI
HSS
SPI
Interface Descriptions
EZ-OTG has a variety of interface options for connectivity, with
several interface options available. See
Table 1
to understand
how the interfaces share pins and can coexist. Below are
some general guidelines:
• I2C EEPROM and OTG do not conflict with any interfaces
• HPI is mutually exclusive to HSS, SPI, and UART
UART
I2C
SCL/SDA
SCL/SDA
OTG
OTGID
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CTS
RTS
RXD
TXD
MOSI
SCK
nSSI
MISO
TX
RX
Document #: 38-08014 Rev. *G
Page 2 of 78
[+] Feedback
CY7C67200
USB Interface
EZ-OTG has two built-in Host/Peripheral SIEs that each have
a single USB transceiver, meeting the USB 2.0 specification
requirements for full and low speed (high speed is not support-
ed). In Host mode, EZ-OTG supports two downstream ports;
each supports control, interrupt, bulk, and isochronous trans-
fers. In Peripheral mode, EZ-OTG supports one peripheral
port with eight endpoints for each of the two SIEs. Endpoint 0
is dedicated as the control endpoint and only supports control
transfers. Endpoints 1 though 7 support Interrupt, bulk (up to
64 bytes per packet), or isochronous transfers (up to 1023
bytes per packet size). EZ-OTG also supports a combination
of Host and Peripheral ports simultaneously, as shown in
Table 2.
Table 2. USB Port Configuration Options
Port Configurations
OTG
OTG + 1 Host
OTG + 1 Peripheral
1 Host + 1 Peripheral
1 Host + 1 Peripheral
2 Hosts
1 Host
1 Host
2 Peripherals
1 Peripheral
1 Peripheral
Port 1A
OTG
OTG
OTG
Host
Peripheral
Host
Host
–
Peripheral
Peripheral
–
Port 2A
–
Host
Peripheral
Peripheral
Host
Host
–
Host
Peripheral
–
Peripheral
OTG Interface
EZ-OTG has one USB port that is compatible with the USB
On-The-Go supplement to the USB 2.0 specification. The USB
OTG port has various hardware features to support Session
Request Protocol (SRP) and Host Negotiation Protocol (HNP).
OTG is only supported on USB PORT 1A.
OTG Features
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V < VBUS < 0.8V
• ID Pin Status
• Switchable 2-Kohm internal discharge resistor on VBUS
• Switchable 500-ohm internal pull-up resistor on VBUS
• Individually switchable internal pull-up and pull-down
resistors on the USB data lines
OTG Pins
Table 4. OTG Interface Pins
Pin Name
DM1A
DP1A
OTGVBUS
OTGID
CSwitchA
CSwitchB
General Purpose IO Interface
Pin Number
F2
E3
C1
F4
D1
D2
USB Features
• USB 2.0 compatible for full and low speed
• Up to two downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must
reside in internal RAM
• Up to eight available peripheral endpoints (1 control
endpoint)
• Supports Control, Interrupt, Bulk, and Isochronous transfers
• Internal DMA channels for each endpoint
• Internal pull up and pull down resistors
• Internal Series termination resistors on USB data lines
USB Pins
Table 3. USB Interface Pins
Pin Name
DM1A
DP1A
DM2A
DP2A
Pin Number
F2
E3
C2
D3
EZ-OTG has up to 25 GPIO signals available. Several other
optional interfaces use GPIO pins as well and may reduce the
overall number of available GPIOs.
GPIO Description
All Inputs are sampled asynchronously with state changes oc-
curring at a rate of up to two 48 MHz clock cycles. GPIO pins
are latched directly into registers, a single flip-flop.
Unused Pin Descriptions
Unused USB pins must be tri-stated with the D+ line pulled
high through the internal pull-up resistor and the D– line pulled
low through the internal pull-down resistor.
Unused GPIO pins must be configured as outputs and driven
low.
UART Interface
EZ-OTG has a built-in UART interface. The UART interface
supports data rates from 900 to 115.2K baud. It can be used
as a development port or for other interface requirements. The
UART interface is exposed through GPIO pins.
Document #: 38-08014 Rev. *G
Page 3 of 78
[+] Feedback
CY7C67200
UART Features
• Supports baud rates of 900 to 115.2K
• 8-N-1
UART Pins
Table 5. UART Interface Pins
Pin Name
TX
RX
I
2
C EEPROM Interface
EZ-OTG provides a master-only I2C interface for external se-
rial EEPROMs. The serial EEPROM can be used to store ap-
plication-specific code and data. This I2C interface is only to
be used for loading code out of EEPROM, it is not a general
I2C interface. The I2C EEPROM interface is a BIOS imple-
mentation and is exposed through GPIO pins. Refer to the
BIOS documentation for additional details on this interface.
I
2
C EEPROM Features
• Supports EEPROMs up to 64 KB (512K bit)
• Auto-detection of EEPROM size
I
2
C EEPROM Pins
Table 6. I
2
C EEPROM Interface Pins
Pin Name
SCK
SDA
LARGE EEPROM
SCK
SDA
Serial Peripheral Interface
EZ-OTG provides an SPI interface for added connectivity.
EZ-OTG may be configured as either an SPI master or SPI
slave. The SPI interface can be exposed through GPIO pins
or the External Memory port.
SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8-byte receive FIFO and 8-byte transmit FIFO
• Selectable master SPI clock rates from 250 kHz to 12 MHz
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz
• Maskable interrupts for block and byte transfer modes
F3
H3
Pin Number
SMALL EEPROM
H3
F3
Pin Number
B5
B4
• Individual bit transfer for non-byte aligned serial communi-
cation in PIO mode
• Programmable delay timing for the active/inactive master
SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
SPI Pins
The SPI port has a few different pin location options as shown
in
Table 7.
The pin location is selectable via the GPIO Control
register [0xC006].
Table 7. SPI Interface Pins
Pin Name
nSSI
SCK
MOSI
MISO
High-Speed Serial Interface
EZ-OTG provides an HSS interface. The HSS interface is a
programmable serial connection with baud rate from 9600
baud to 2M baud. The HSS interface supports both byte and
block mode operations as well as hardware and software
handshaking. Complete control of EZ-OTG can be accom-
plished through this interface via an extensible API and com-
munication protocol. The HSS interface can be exposed
through GPIO pins or the External Memory port.
HSS Features
• 8-bit, no parity code
• Programmable baud rate from 9600 baud to 2M baud
• Selectable 1- or 2-stop bit on transmit
• Programmable intercharacter gap timing for Block Transmit
• 8-byte receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-OTG internal
memory (DMA transfer)
• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done
interrupts
• Complete access to internal memory
HSS Pins
Table 8. HSS Interface Pins
Pin Name
CTS
RTS
RX
TX
Pin Number
F6
E4
E5
E6
Pin Number
F6 or C6
D5
D4
C5
Document #: 38-08014 Rev. *G
Page 4 of 78
[+] Feedback
CY7C67200
Host Port Interface (HPI)
EZ-OTG has an HPI interface. The HPI interface provides
DMA access to the EZ-OTG internal memory by an external
host, plus a bidirectional mailbox register for supporting
high-level communication protocols. This port is designed to
be the primary high-speed connection to a host processor.
Complete control of EZ-OTG can be accomplished through
this interface via an extensible API and communication
protocol. Other than the hardware communication protocols, a
host processor has identical control over EZ-Host whether
connecting to the HPI or HSS port. The HPI interface is
exposed through GPIO pins.
Note
It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as
outputs for a test mode. If these pins need to be used as inputs,
a series resistor is required (10 ohm to 48 ohm is recom-
mended). Refer to BIOS documentation for addition details.
See section “Reset Pin” on page 9.
HPI Features
• 16-bit data bus interface
• 16 MB/s throughput
• Auto-increment of address pointer for fast block mode
transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status register
HPI Pins
Table 9. HPI Interface Pins
Pin Name
INT
nRD
nWR
nCS
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
[1, 2]
Table 9. HPI Interface Pins
[1, 2]
(continued)
Pin Name
D7
D6
D5
D4
D3
D2
D1
D0
Pin Number
B5
B4
C4
B3
A3
C3
A2
B2
The two HPI address pins are used to address one of four
possible HPI port registers as shown in
Table 10
below.
Table 10.HPI Addressing
HPI A[1:0]
HPI Data
HPI Mailbox
HPI Address
HPI Status
Charge Pump Interface
VBUS for the USB On-The-Go (OTG) port can be produced by
EZ-OTG using its built-in charge pump and some external
components. The circuit connections should look similar to
Figure 1
below.
Figure 1. Charge Pump
D1
CSWITCHA
A1
0
0
1
1
A0
0
1
0
1
D2
Pin Number
H4
G4
H5
G5
H6
F5
F6
E4
E5
E6
D4
D5
C6
C5
CY7C67200
CSWITCHB
C1
OTGVBUS
VBUS
C2
Component details:
• D1 and D2: Schottky diodes with a current rating greater
than 60 mA.
• C1: Ceramic capacitor with a capacitance of 0.1 µF.
• C2: Capacitor value must be no more that 6.5 µF since that
is the maximum capacitance allowed by the USB OTG
specification for a dual-role device. The minimum value of
C2 is 1 µF. There are no restrictions on the type of capacitor
for C2.
If the VBUS charge pump circuit is not to be used,
CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon-
nected.
Notes
1. HPI_INT is for the Outgoing Mailbox Interrupt.
2. HPI strobes are negative logic sampled on rising edge.
Document #: 38-08014 Rev. *G
Page 5 of 78
[+] Feedback
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
