CY7C60445, CY7C6045x
enCoRe™ V Low Voltage Microcontroller
Features
■
Powerful Harvard Architecture Processor
❐
M8C processor speeds running up to 24 MHz
❐
Low power at high processing speeds
❐
Interrupt controller
❐
1.71V to 3.6V operating voltage
❐
Temperature range: 0°C to 70°C
Flexible On-Chip Memory
❐
Up to 32K Flash program storage
50,000 Erase/write cycles
❐
Up to 2048 bytes SRAM data storage
❐
Flexible protection modes
❐
In-System Serial Programming (ISSP)
Complete Development Tools
❐
Free development tool (PSoC Designer™)
❐
Full featured, in-circuit emulator and programmer
❐
Full speed emulation
❐
Complex breakpoint structure
❐
128K trace memory
Precision, Programmable Clocking
❐
Crystal-less oscillator with support for an external crystal or
resonator
❐
Internal ±5.0% 6, 12, or 24 MHz main oscillator
❐
Internal low speed oscillator at 32 kHz for watchdog and
sleep.The frequency range is 19–50 kHz with a 32 kHz typical
value
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■
Programmable Pin Configurations
❐
25 mA sink current on all GPIO
❐
Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐
Configurable inputs on all GPIO
❐
Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/O pins
❐
Selectable, regulated digital IO on Port 1
• Configurable input threshold for Port 1
• 3.0V, 20 mA total Port 1 source current
• Hot-swappable
❐
5 mA strong drive mode on Ports 0 and 1
Additional System Resources
❐
Configurable communication speeds
2
❐
I C™ Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
❐
SPI™ master and SPI slave
• Configurable between 93.75 kHz and 12 MHz
❐
Three 16-bit timers
❐
8-bit ADC used to monitor battery voltage or other signals -
with external components
❐
Watchdog and sleep timers
❐
Integrated supervisory circuit
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enCoRe V LV Block Diagram
enCoRe V
Low Voltage
CORE
Port 4
Port 3
Port 2
Port 1
Port 0
Prog. LDO
System Bus
SRAM
2048 Bytes
Interrupt
Controller
SROM
Flash 32K
Sleep and
Watchdog
CPU Core
(M8C)
6/12/24 MHz Internal Main Oscillator
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-12395 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 7, 2008
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Functional Overview
The enCoRe V LV family of devices are designed to replace
multiple traditional low voltage microcontroller system compo-
nents with one, low cost single chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, Flash
program memory, SRAM data memory, and configurable IO are
included in a range of convenient pinouts.
The architecture for this device family, as illustrated in enCoRe
V LV Block Diagram, is comprised of two main areas: the CPU
core and the system resources. Depending on the enCoRe V LV
package, up to 36 general purpose IO (GPIO) are also included.
Enhancements over the Cypress’ legacy low voltage microcon-
trollers include faster CPU at lower voltage operation, lower
current consumption, twice the RAM and Flash, hot-swapable
IOs, I2C hardware address recognition, new very low current
sleep mode, and new package options.
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The 5V maximum input, 1.8, 2.5, or 3V selectable output, low
dropout regulator (LDO) provides regulation for IOs. A register
controlled bypass mode allows the user to disable the LDO.
Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V LV family of parts.
■
Getting Started
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, reference the
PSoC
Mixed-Signal Array Technical Reference Manual,
which can be
found on
http://www.cypress.com/psoc.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest PSoC device data sheets on the
web at
http://www.cypress.com.
The enCoRe V LV Core
The enCoRe V LV Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as a
configurable I2C slave and SPI master-slave communication
interface and various system resets supported by the M8C.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/shop/.
Under Product Categories click
PSoC® Mixed Signal Arrays to view a current list of available
items.
Technical Training Modules
Free PSoC technical training modules are available for users
new to PSoC. Training modules cover designing, debugging,
advanced analog and CapSense. Go to
http://www.cypress.com/techtrain.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. Brief statements describing the merits of each system
resource are presented below.
■
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to
http://www.cypress.com,
click on Support
located at the top of the web page, and select CYPros
Consultants.
10-bit on-chip ADC shared between System Performance
manager (used to calculate parameters based on temperature
for flash write operations) and the user.
The I2C slave and SPI master-slave module provides 50, 100,
or 400 kHz communication over two wires. SPI communication
over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
In I2C slave mode the hardware address recognition feature
reduces the already low power consumption by eliminating the
need for CPU intervention until a packet addressed to the target
device has been received.
Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
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Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four hour guaranteed
response at
http://www.cypress.com/support.
■
Application Notes
A long list of application notes assists you in every aspect of your
design effort. To view the PSoC application notes, go to the
http://www.cypress.com
web site and select Application Notes
under the Documentation list located at the top of the web page.
■
Document Number: 001-12395 Rev. *G
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Development Tools
PSoC Designer™ is a Microsoft
®
Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers.
The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers.
C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC Mixed-Signal Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12395 Rev. *G
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the IO pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an
analog-to-digital converter (ADC) to convert the potentiometer’s
output to a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
(I
2
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed-signal
varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-12395 Rev. *G
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym
API
CPU
GPIO
GUI
ICE
ILO
IMO
IO
LSb
LVD
MSb
POR
PPOR
PSoC®
SLIMO
SRAM
Description
application programming interface
central processing unit
general purpose IO
graphical user interface
in-circuit emulator
internal low speed oscillator
internal main oscillator
input/output
least significant bit
low voltage detect
most significant bit
power on reset
precision power on reset
Programmable System-on-Chip™
slow IMO
static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
section.
Table 6 on page 13
lists all the abbreviations used to
measure the enCoRe V LV devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 001-12395 Rev. *G
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