CY7C601xx, CY7C602xx
enCoRe™ II Low-Voltage Microcontroller
1. Features
enCoRe II low-voltage (enCoRe II LV) – enhanced
component reduction
❐
Internal crystalless oscillator with support for optional
external clock or external crystal or resonator
❐
Configurable I/O for real world interface without external
components
■
Enhanced 8-bit microcontroller
❐
Harvard architecture
❐
M8C CPU speed up to 12 MHz or sourced by an external
crystal, resonator, or clock signal
■
Internal memory
❐
256 bytes of random access memory (RAM)
❐
8 KB of flash including electrically erasable read only memory
(EEROM) emulation
■
Low power consumption
❐
Typically 2.25 mA at 3 MHz
❐
5
A
sleep
■
In-system reprogrammability
❐
Enables easy firmware update
■
General-purpose I/O (GPIO) ports
❐
Up to 36 GPIO pins
❐
2-mA source current on all GPIO pins
❐
Configurable 8 or 50 mA per pin current sink on designated
pins
❐
Each GPIO port supports high-impedance inputs,
configurable pull-up, open drain output, complementary
metal oxide semiconductor (CMOS), and
transistor-transistor logic (TTL) inputs, and CMOS output
❐
Maskable interrupts on all I/O pins
■
■
■
■
■
■
■
■
■
■
■
■
■
■
SPI serial communication
❐
Master or slave operation
❐
Configurable up to 2 Mbit per second transfers
❐
Supports half-duplex single-data line mode for optical
sensors
2-channel 8-bit or 1-channel 16-bit capture timer registers,
which store both rising and falling edge times
❐
Two registers each for two input pins
❐
Separate registers for rising and falling edge capture
❐
Simplifies interface to radio frequency (RF) inputs for wireless
applications
Internal low-power wakeup timer during suspend mode
❐
Periodic wakeup with no external components
Programmable interval timer interrupts
Reduced RF emissions at 27 MHz and 96 MHz
Watchdog timer (WDT)
Low-voltage detection (LVD) with user-selectable threshold
voltages
Improved output drivers to reduce electromagnetic interference
(EMI)
Operating voltage from 2.7 V to 3.6 V DC
Operating temperature from 0 °C to 70 °C
Available in 40-pin plastic dual inline package (PDIP), 24-pin
small outline integrated circuit (SOIC), 24-pin quad small
outline package (QSOP) and shrink small outline package
(SSOP), 48-pin SSOP
Advanced development tools based on Cypress PSoC
®
tools
Industry-standard programmer support
2. Logic Block Diagram
Interrupt
Control
4 SPI/GPIO
Pins
16 Extended
I/O Pins
16 GPIO
Pins
Wakeup
Timer
Internal
12 MHz
Oscillator
Clock
Control
Crystal
Oscillator
CY7C601xx only
M8C CPU
RAM
256 Byte
Flash
8 KB
12-bit Timer
Capture
Timers
POR /
Low-Voltage
Detect
V
DD
Watchdog
Timer
Cypress Semiconductor Corporation
Document 38-16016 Rev. *J
•198 Champion Court
•San Jose, CA 95134-1709
•408-943-2600
Revised June 6, 2011
CY7C601xx, CY7C602xx
3. Contents
Applications ...................................................................... 3
Introduction ....................................................................... 3
Conventions ...................................................................... 3
Pinouts .............................................................................. 4
Pin Assignments .......................................................... 5
Register Summary ............................................................ 7
CPU Architecture .............................................................. 9
CPU Registers ................................................................... 9
Flags Register ............................................................. 9
Addressing Modes ..................................................... 11
Instruction Set Summary ............................................... 13
Memory Organization ..................................................... 15
Flash Program Memory Organization ....................... 15
Data Memory Organization ....................................... 16
Flash .......................................................................... 16
SROM ........................................................................ 16
SROM Function Descriptions .................................... 17
SROM Table Read Description ................................. 20
Clocking .......................................................................... 22
Trim Values for the IOSCTR Register ....................... 22
Clock Architecture Description .................................. 23
CPU Clock During Sleep Mode ................................. 30
Reset ................................................................................ 31
Power On Reset ........................................................ 32
Watchdog Timer Reset .............................................. 32
Sleep Mode ...................................................................... 32
Sleep Sequence ........................................................ 33
Wakeup Sequence .................................................... 34
Low-Voltage Detect Control ......................................... 35
POR Compare State ................................................. 36
ECO Trim Register .................................................... 36
General-Purpose I/O Ports ............................................. 37
Port Data Registers ................................................... 37
GPIO Port Configuration ........................................... 38
Serial Peripheral Interface (SPI) .................................... 45
SPI Data Register ...................................................... 46
SPI Configure Register ............................................. 46
SPI Interface Pins ...................................................... 48
Timer Registers .............................................................. 48
Registers ................................................................... 48
Interrupt Controller ......................................................... 55
Architectural Description ........................................... 56
Interrupt Processing .................................................. 56
Interrupt Latency ....................................................... 56
Interrupt Registers ..................................................... 57
Absolute Maximum Ratings .......................................... 60
DC Characteristics .................................................... 60
AC Characteristics .................................................... 61
Ordering Information ...................................................... 64
Package Handling ........................................................... 64
Package Diagrams .......................................................... 65
Document History Page ................................................. 67
Sales, Solutions, and Legal Information ...................... 68
Document 38-16016 Rev. *J
Page 2 of 68
CY7C601xx, CY7C602xx
4. Applications
The CY7C601xx and CY7C602xx are targeted for the following
applications:
■
PC wireless human interface devices (HID)
❐
Mice (optomechanical, optical, trackball)
❐
Keyboards
❐
Presenter tools
Gaming
❐
Joysticks
❐
Gamepad
General-purpose wireless applications
❐
Remote controls
❐
Barcode scanners
❐
POS terminal
❐
Consumer electronics
❐
Toys
■
In addition, enCoRe II LV includes a WDT, a vectored interrupt
controller, a 16-bit free-running timer with capture registers, and
a 12-bit programmable interval timer. The power on reset (POR)
circuit detects when power is applied to the device, resets the
logic to a known state, and executes instructions at flash address
0x0000. When power falls below a programmable trip voltage, it
generates a reset or is configured to generate an interrupt. There
is a LVD circuit that detects when V
CC
drops below a
programmable trip voltage. This is configurable to generate a
LVD interrupt to inform the processor about the low-voltage
event. POR and LVD share the same interrupt; there is no
separate interrupt for each. The WDT ensures the firmware
never gets stalled in an infinite loop.
The microcontroller supports 17 maskable interrupts in the
vectored interrupt controller. All interrupts can be masked.
Interrupt sources include LVR or POR, a programmable interval
timer, a nominal 1.024 ms programmable output from the
free-running timer, two capture timers, five GPIO ports, three
GPIO pins, two SPI, a 16-bit free-running timer wrap, and an
internal wakeup timer interrupt. The wakeup timer causes
periodic interrupts when enabled. The capture timers interrupt
whenever a new timer value is saved due to a selected GPIO
edge event. A total of eight GPIO interrupts support both TTL or
CMOS thresholds. For additional flexibility, on the edge-sensitive
GPIO pins, the interrupt polarity is programmable to be either
rising or falling.
The free-running timer generates an interrupt at 1024-s rate. It
also generates an interrupt when the free-running counter
overflow occurs – every 16.384 ms. The duration of an event
under firmware control is measured by reading the timer at the
start and end of an event, then calculating the difference
between the two values. The two 8-bit capture timer registers
save a programmable 8-bit range of the free-running timer when
a GPIO edge occurs on the two capture pins (P0.5 and P0.6).
The two 8-bit capture registers are ganged into a single 16-bit
capture register.
The enCoRe II LV supports in-system programming by using the
P1.0 and P1.1 pins as the serial programming mode interface.
■
5. Introduction
The enCoRe II LV family brings the features and benefits of the
enCoRe II to non-USB applications. The enCoRe II family has
an integrated oscillator that eliminates the external crystal or
resonator, reducing overall cost. Other external components,
such as wakeup circuitry, are also integrated into this chip.
The enCoRe II LV is a low-voltage, low-cost 8-bit
flash-programmable microcontroller.
The enCoRe II LV features up to 36 GPIO pins. The I/O pins are
grouped into five ports (Port 0 to 4). The pins on ports 0 and 1
are configured individually, when the pins on ports 2, 3, and 4 are
only configured as a group. Each GPIO port supports
high-impedance inputs, configurable pull-up, open-drain output,
CMOS, and TTL inputs, and CMOS output with up to five pins
that support programmable drive strength of up to 50-mA sink
current. Additionally, each I/O pin is used to generate a GPIO
interrupt to the microcontroller. Each GPIO port has its own GPIO
interrupt vector with the exception of GPIO port 0. GPIO port 0
has, in addition to the port interrupt vector, three dedicated pins
that have independent interrupt vectors (P0.2–P0.4).
The enCoRe II LV features an internal oscillator. Optionally, an
external 1-MHz to 24-MHz crystal is used to provide a higher
precision reference. The enCoRe II LV also supports external
clock.
The enCoRe II LV has 8 KB of flash for user code and 256 bytes
of RAM for stack space and user variables.
6. Conventions
In this document, bit positions in the registers are shaded to
indicate which members of the enCoRe II LV family implement
the bits.
Available in all enCoRe II LV family members
CY7C601xx only
Document 38-16016 Rev. *J
Page 3 of 68
CY7C601xx, CY7C602xx
7. Pinouts
Figure 7-1. Package Configurations
Top View
CY7C60223
24-Pin SOIC
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
CLKOUT\P0.1
CLKIN\P0.0
P2.1
P2.0
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2
V
DD
P1.1
P1.0
CY7C60223
24-Pin QSOP
NC
P0.7
TIO1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
CLKOUT\P0.1
CLKIN\P0.0
P2.1
P2.0
NC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P3.1
P3.0
P1.3/SSEL
P1.2
V
DD
P1.1
P1.0
V
SS
CY7C60123
40-Pin PDIP
V
DD
P4.1
P4.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P0.7
T1O1/P0.6
TIO0/P0.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
CLKOUT/P0.1
CLKIN/P0.0
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
P4.3
P4.2
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
V
DD
P1.1
P1.0
CY7C60123
48-Pin SSOP
NC
NC
NC
NC
V
DD
P4.1
P4.0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P0.7
TIO1/P0.6
TIO0/PO.5
INT2/P0.4
INT1/P0.3
INT0/P0.2
CLKOUT/P0.1
CLKIN/P0.0
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
V
SS
P4.3
P4.2
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P1.7
P1.6/SMISO
P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
V
DD
P1.1
P1.0
Document 38-16016 Rev. *J
Page 4 of 68
CY7C601xx, CY7C602xx
7.1 Pin Assignments
Table 7-1. Pin Assignments
48
40
24
24
SSOP PDIP QSOP SOIC
7
6
42
43
34
35
36
37
38
39
40
41
15
14
13
12
11
10
9
8
25
3
2
38
39
30
31
32
33
34
35
36
37
11
10
9
8
7
6
5
4
21
–
–
–
–
19
20
–
–
–
–
–
–
11
10
–
–
–
–
–
–
14
–
–
–
–
18
19
–
–
–
–
–
–
11
10
–
–
–
–
–
–
13
Name
P4.0
P4.1
P4.2
P4.3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
GPIO port 1 bit 0/ISSP-SCLK
If this pin is used as a general-purpose output it draws current. It is, therefore,
configured as an input to reduce current draw.
GPIO port 1 bit 1/ISSP-SDATA
If this pin is used as a general-purpose output it draws current. It is, therefore,
configured as an input to reduce current draw.
GPIO port 1 bit 2
GPIO port 1 bit 3—Configured individually
Alternate function is SSEL signal of the SPI bus.
GPIO port 1 bit 4—Configured individually
Alternate function is SCLK signal of the SPI bus.
GPIO port 1 bit 5—Configured individually
Alternate function is SMOSI signal of the SPI bus.
GPIO port 1 bit 6—Configured individually
Alternate function is SMISO signal of the SPI bus.
GPIO port 1 bit 7—Configured individually
TTL voltage threshold.
GPIO port 0 bit 0—Configured individually
On CY7C601xx, optional Clock In when external oscillator is disabled or external
oscillator input when external oscillator is enabled.
On CY7C602xx, oscillator input when configured as Clock In.
GPIO port 2—configured as a group (byte)
GPIO port 3—configured as a group (byte)
Description
GPIO port 4—configured as a group (nibble)
26
22
15
14
P1.1
28
29
30
31
32
33
23
24
25
26
27
28
29
19
17
18
21
22
23
24
9
16
17
20
21
22
23
9
P1.2
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
P1.7
P0.0/CLKIN
Document 38-16016 Rev. *J
Page 5 of 68
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