1CY 7C33 5
fax id: 6018
CY7C335
Universal Synchronous EPLD
Features
• 100-MHz output registered operation
• Twelve I/O macrocells, each having:
— Registered, three-state I/O pins
— Input and output register clock select multiplexer
— Feed back multiplexer
•
•
•
•
•
•
•
•
•
•
— Output enable (OE) multiplexer
Bypass on input and output registers
All twelve macrocell state registers can be hidden
User configurable I/O macrocells to implement JK or
RS flip-flops and T or D registers
Input multiplexer per pair of I/O macrocells allows I/O
pin associated with a hidden macrocell state register
to be saved for use as an input
Four dedicated hidden registers
Twelve dedicated registered inputs with individually
programmable bypass option
Three separate clocks—two input clocks, two output
clocks
Common (pin 14-controlled) or product term-controlled
output enable for each I/O pin
256 product terms—32 per pair of macrocells, variable
distribution
Global, synchronous, product term-controlled, state
register set and reset—inputs to product term are
clocked by input clock
— 2-ns input set-up and 9-ns output register clock to
output
— 10-ns input register clock to state register clock
• 28-pin, 300-mil DIP, LCC, PLCC
• Erasable and reprogrammable
• Programmable security bit
Functional Description
The CY7C335 is a high-performance, erasable, programma-
ble logic device (EPLD) whose architecture has been opti-
mized to enable the user to easily and efficiently construct very
high performance state machines.
The architecture of the CY7C335, consisting of the user-con-
figurable output macrocell, bidirectional I/O capability, input
registers, and three separate clocks, enables the user to de-
sign high-performance state machines that can communicate
either with each other or with microprocessors over bidirec-
tional parallel buses of user-definable widths.
The four clocks permit independent, synchronous state ma-
chines to be synchronized to each other.
The user-configurable macrocells enable the designer to des-
ignate JK-, RS-, T-, or D-type devices so that the number of
product terms required to implement the logic is minimized.
The CY7C335 is available in a wide variety of packages in-
cluding 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and
LCCs.
Logic Block Diagram
OE/I
11
14
I
10
13
I
9
12
I
8
11
I
7
10
I
6
9
V
SS
8
I
5
7
I
4
6
I
3
5
I
2
4
I
1
/CLK3
3
I
0
/CLK2
2
CLK1
1
PROGRAMMABLE AND ARRAY
(258x68)
9
19
11
17
13
15
13
17
11
19
15
13
17
11
19
9
15
I/O
11
16
I/O
10
17
I/O
9
18
I/O
8
19
I/O
7
20
I/O
6
21
V
SS
22
V
CC
23
I/O
5
24
I/O
4
25
I/O
3
26
I/O
2
27
I/O
1
28
I/O
0
C335–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
July 1991 – Revised March 26, 1997
CY7C335
Pin Configurations
LCC
Top View
PLCC
Top View
4 3 2 1 282726
I
3
I
4
I
5
V
SS
I
6
I
7
I
8
5
6
7
8
9
10
11
12131415161718
C335–2
25
24
23
22
21
20
19
I/O
3
I/O
4
I/O
5
V
CC
V
SS
I/O
6
I/O
7
I
3
I
4
I
5
V
SS
I
6
I
7
I
8
5
6
7
8
9
10
11
4 3 2 1 2827 26
25
24
23
22
21
20
19
I/O
3
I/O
4
I/O
5
V
CC
V
SS
I/O
6
I/O
7
121314 1516 1718
C335–3
Selection Guide
CY7C335–100
Maximum Operating
Frequency (MHz)
I
CC1
(mA)
Commercial
Military
Commercial
Military
140
100
CY7C335–83
83.3
83.3
140
160
CY7C335–66
66.6
66.6
140
160
CY7C335–50
50
50
140
160
Architecture Configuration Bits
The architecture configuration bits are used to program the
multiplexers. The function of the architecture bits is outlined in
Table 1.
Table 1. Architecture Configuration Bits
Architecture
Configuration Bit
C0
C1
Output Enable
Select MUX
State Register
Feed Back MUX
I/O Macrocell
Input Register
Clock Select
MUX
Input Register
Bypass MUX—
I/O Macrocell
Output Register
Bypass MUX
State Clock MUX
Number of Bits
12 Bits, 1 Per
I/O Macrocell
12 Bits, 1 Per
I/O Macrocell
12 Bits, 1 Per
I/O Macrocell
Value
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
12 Bits, 1 Per
I/O Macrocell
12 Bits, 1 Per
I/O Macrocell
16 Bits, 1 Per I/O
Macrocell and 1 Per
Hidden Macrocell
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
Function
Output Enable Controlled by Product Term
Output Enable Controlled by Pin 14
State Register Output is Fed Back to Input Array
I/O Macrocell is Configured as an Input and
Output of Input Path is Fed to Array
ICLK1 Controls the Input Register I/O Macrocell
Input Register Clock Input
ICLK2 Controls the Input Register I/O Macrocell
Input Register Clock Input
Selects Input to Feedback MUX from Input
Register
Selects Input to Feedback MUX from I/O pin
Selects Output from the State Register
Selects Output from the Array, Bypassing the
State Register
State Clock 1 Controls the State Register
State Clock 2 Controls the State Register
C2
C3
C4
C5
2
CY7C335
Table 1. Architecture Configuration Bits
(continued)
Architecture
Configuration Bit
C6
Dedicated Input
Register Clock
Select MUX
Input Register
Bypass MUX—
Input Cell
ICLK2 Select
MUX
ICLK1 Select
MUX
SCLK2 Select
MUX
I/O Macrocell
Pair Input
Select MUX
Number of Bits
12 Bits, 1 Per
Dedicated Input
Cell
12 Bits, 1 Per
Dedicated Input
Cell
1 Bit
1 Bit
1 Bit
6 Bits, 1 Per
I/O Macrocell
Pair
Value
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
0—Virgin State
1—Programmed
Function
ICLK1 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
ICLK2 Controls the Input Register I/O Macrocell
Dedicated Input Register Clock Input
Selects Input to Array from Input Register
Selects Input to Array from Input Pin
Input Clock 2 Controlled by Pin 2
Input Clock 2 Controlled by Pin 3
Input Clock 1 Controlled by Pin 2
Input Clock 1 Controlled by Pin 1
State Clock 2 Grounded
State Clock 2 Controlled by Pin 3
Selects Data from I/O Macrocell Input Path of
Macrocell A of Macrocell Pair
Selects Data from I/O Macrocell Input Path of
Macrocell B of Macrocell Pair
C7
C8
C9
C10
CX
(11–16)
1
INPUTREGISTER
INPUT
PIN
0
D
Q
INPUT
REG
BYPASS
MUX
TO ARRAY
ICLK1
ICLK2
0
INPUT
CLOCK
1
MUX
C7
C6
C335–4
Figure 1. CY7C335 Input Macrocell
3
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