CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
72-Mbit QDR
®
II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■
Configurations
With Read Cycle Latency of 2.5 cycles
CY7C1561KV18: 8M ×8
CY7C1576KV18: 8M × 9
CY7C1565KV18: 2M × 36
Separate independent read and write data ports
❐
Supports concurrent transactions
550-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
Available in 2.5-clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
Quad data rate (QDR
®
) II+ operates with 2.5-cycle read latency
when DOFF is asserted HIGH
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
Available in ×8, ×9, and ×36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8 V± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD [1]
❐
Supports both 1.5 V and 1.8 V I/O supply
High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
■
■
■
■
■
Functional Description
The CY7C1561KV18, CY7C1576KV18, and CY7C1565KV18
are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+ archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turnaround” the data bus that exists with
common I/O devices. Each port is accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II+ read and write ports are completely independent
of one another. To maximize data throughput, both read and write
ports are equipped with DDR interfaces. Each address location
is associated with four 8-bit words (CY7C1561KV18), 9-bit
words (CY7C1576KV18), or 36-bit words (CY7C1565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
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Selection Guide
Description
Maximum operating frequency
Maximum operating current
×8
×9
×36
550 MHz
550
900
900
1310
500 MHz
500
830
830
1210
450 MHz
450
760
760
1100
400 MHz
400
690
690
1000
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-15878 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 10, 2011
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CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
Logic Block Diagram (CY7C1561KV18)
D
[7:0]
8
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
21
A
(20:0)
2M
×
8 Array
2M
×
8 Array
2M
×
8 Array
2M
×
8 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
32
V
REF
WPS
NWS
[1:0]
16
Control
Logic
16
Reg.
Reg.
Reg. 8
8
8
8
CQ
8
Q
[7:0]
QVLD
Logic Block Diagram (CY7C1576KV18)
D
[8:0]
9
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
21
A
(20:0)
2M
×
9 Array
2M
×
9 Array
2M
×
9 Array
2M
×
9 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
36
V
REF
WPS
BWS
[0]
18
Control
Logic
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q
[8:0]
QVLD
Document Number: 001-15878 Rev. *L
Page 2 of 29
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CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
Logic Block Diagram (CY7C1565KV18)
D
[35:0]
36
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Write
Reg
Address
Register
Write
Reg
Write
Reg
Write
Reg
Address
Register
19
A
(18:0)
512K
×
36 Array
512K
×
36 Array
512K
×
36 Array
512K
×
36 Array
K
K
CLK
Gen.
Control
Logic
RPS
DOFF
Read Data Reg.
CQ
144
V
REF
WPS
BWS
[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
QVLD
Document Number: 001-15878 Rev. *L
Page 3 of 29
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CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
Contents
Pin Configuration ............................................................. 5
165-Ball FBGA (13 × 15 × 1.4 mm) Pinout.................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD)...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO)................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ...............................
TAP Timing and Test Conditions ..................................
Identification Register Definitions ................................
Scan Register Sizes .......................................................
Instruction Codes ...........................................................
Boundary Scan Order ....................................................
Power-Up Sequence in QDR II+ SRAM .........................
Power-Up Sequence .................................................
PLL Constraints.........................................................
Maximum Ratings...........................................................
Operating Range.............................................................
Neutron Soft Error Immunity .........................................
Electrical Characteristics...............................................
DC Electrical Characteristics.....................................
AC Electrical Characteristics .....................................
Capacitance ....................................................................
Thermal Resistance........................................................
Switching Characteristics..............................................
Switching Waveforms ....................................................
Read/Write/Deselect Sequence ................................
Ordering Information......................................................
Ordering Code Definition...........................................
Package Diagram............................................................
Acronyms ........................................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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Document Number: 001-15878 Rev. *L
Page 4 of 29
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CY7C1561KV18
CY7C1576KV18
CY7C1565KV18
Pin Configuration
165-Ball FBGA (13
×
15
×
1.4 mm) Pinout
CY7C1561KV18 (8M × 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1576KV18 (8M × 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
QVLD
NC
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
RPS
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-15878 Rev. *L
Page 5 of 29
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