CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
72-Mbit DDR II SRAM 2-Word
Burst Architecture
Features
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Functional Description
The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and
CY7C1520KV18 are 1.8 V synchronous pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1516KV18
and two 9-bit words in the case of CY7C1527KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1516KV18 and
CY7C1527KV18. On CY7C1518KV18 and CY7C1520KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518KV18 and two 36-bit words in the case of
CY7C1520KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
333 MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with 1 cycle read latency when
DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–V
DD
)
❐
Supports both 1.5 V and 1.8 V IO supply
Available in 165-ball fine pitch ball grid array (FBGA) package
(13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible Test Access Port
Phase-locked loop (PLL) for accurate data placement
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Configurations
CY7C1516KV18 – 8M x 8
CY7C1527KV18 – 8M x 9
CY7C1518KV18 – 4M x 18
CY7C1520KV18 – 2M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
333 MHz
333
510
510
520
640
300 MHz
300
480
480
490
600
250 MHz
250
420
420
430
530
200 MHz
200
370
370
380
450
167 MHz
167
340
340
340
400
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-00437 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 10, 2011
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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Logic Block Diagram (CY7C1516KV18)
A
(21:0)
LD
K
K
DOFF
22
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
4M x 8 Array
Write
Reg
8
4M x 8 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
Read Data Reg.
16
Control
Logic
V
REF
R/W
NWS
[1:0]
8
8
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
DQ
[7:0]
Logic Block Diagram (CY7C1527KV18)
A
(21:0)
LD
K
K
DOFF
22
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
4M x 9 Array
Write
Reg
9
4M x 9 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
Read Data Reg.
18
Control
Logic
V
REF
R/W
BWS
[0]
9
9
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
DQ
[8:0]
Document Number: 001-00437 Rev. *J
Page 2 of 33
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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Logic Block Diagram (CY7C1518KV18)
A0
Burst
Logic
A
(21:0)
22
LD
K
K
21
Write Add. Decode
Read Add. Decode
A
(21:1)
Address
Register
Write
Reg
2M x 18 Array
Write
Reg
18
2M x 18 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
36
Control
Logic
V
REF
R/W
BWS
[1:0]
18
18
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ
[17:0]
Logic Block Diagram (CY7C1520KV18)
A0
Burst
Logic
A
(20:0)
21
LD
K
K
20
Write Add. Decode
Read Add. Decode
A
(20:1)
Address
Register
Write
Reg
1M x 36 Array
Write
Reg
36
1M x 36 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
72
Control
Logic
V
REF
R/W
BWS
[3:0]
36
36
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ
[35:0]
Document Number: 001-00437 Rev. *J
Page 3 of 33
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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Contents
Pin Configuration ............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
DDR Operation............................................................ 9
Depth Expansion ......................................................... 9
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Burst Address Table
(CY7C1518KV18, CY7C1520KV18) ................................ 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO)................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ...............................
TAP Timing and Test Conditions ..................................
Identification Register Definitions ................................
Scan Register Sizes .......................................................
Instruction Codes...........................................................
Boundary Scan Order ....................................................
Power Up Sequence in DDR II SRAM ...........................
Power Up Sequence .................................................
PLL Constraints.........................................................
Maximum Ratings...........................................................
Operating Range ............................................................
Neutron Soft Error Immunity.........................................
Electrical Characteristics ..............................................
DC Electrical Characteristics.....................................
AC Electrical Characteristics.....................................
Capacitance ....................................................................
Thermal Resistance .......................................................
Switching Characteristics .............................................
Switching Waveforms ....................................................
Ordering Information ....................................................
Ordering Code Definition...........................................
Package Diagram ...........................................................
Acronyms........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page.................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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Document Number: 001-00437 Rev. *J
Page 4 of 33
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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Pin Configuration
The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1516KV18 (8M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
CY7C1527KV18 (8M x 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00437 Rev. *J
Page 5 of 33
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