Output Current into Outputs (LOW) .............................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Military
[1]
Ambient
Temperature
0
°
C to +70
°
C
−55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
Note:
1. T
A
is the “instant on” case temperature.
Electrical Characteristics
Over the Operating Range
[2]
7C150
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH Voltage
Output LOW Current
Input HIGH Level
Input LOW Level
Input Load Current
Output Current (High Z)
Output Short Circuit Current
[3]
V
CC
Operating Supply Current
GND < V
I
< V
CC
V
OL
< V
OUT
< V
OH
,
Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Commercial
Military
Test Conditions
V
CC
= Min., I
OH
=
−
0.4 mA
V
CC
= Min., I
OL
= 12 mA
2.0
−3.0
−10
−50
Min.
2.4
0.4
V
CC
0.8
+10
+50
−300
90
100
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than 1 output should be shorted at a time. Duration of the short circuit should not exceed 30 seconds.
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1329
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
202
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R1329
Ω
ALL INPUT PULSES
R2
202
Ω
3.0V
10%
GND
< 3 ns
(b)
C150–3
90%
90%
10%
< 3 ns
C150–4
(a)
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
125
Ω
1.9V
Document #: 38-05024 Rev. *A
Page 2 of 11
CY7C150
Switching Characteristics
Over the Operating Range
[2,5]
7C150−10
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
LZCS
t
HZCS
t
DOE
t
LZOE
t
HZOE
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
RRC
t
SAR
t
SWER
t
SCSR
t
PRS
t
HCSR
t
HWER
t
HAR
t
LZRS
t
HZRS
Read Cycle Time
Address to Data Valid
Output Hold from Address
Change
CS LOW to Data Valid
CS LOW to Low Z
[6]
CS HIGH to High Z
[6,7]
OE LOW to Data Valid
OE LOW to Low Z
[6]
7C150−12
Min.
12
Max.
7C150−15
Min.
15
Max.
7C150−25
Min.
25
Max.
7C150−35
Min.
35
Max.
Unit
ns
35
2
ns
ns
20
0
25
20
0
25
35
20
30
5
5
20
20
5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
70
0
0
0
30
0
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
Description
Min.
10
Max.
10
2
8
0
6
6
0
6
10
6
8
2
2
6
6
2
0
6
20
0
0
0
10
0
8
10
0
6
24
0
0
0
12
0
12
12
0
12
8
10
2
2
8
8
2
0
0
0
2
12
2
10
0
8
8
0
8
15
11
13
2
2
11
11
2
0
8
30
0
0
0
15
0
15
15
0
8
15
2
12
0
11
10
0
9
25
15
20
5
5
15
15
5
0
12
50
0
0
0
20
0
30
30
0
12
25
15
20
15
20
OE HIGH to High Z
[6,7]
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6,7]
Reset Cycle Time
Address Valid to Beginning of
Reset
Write Enable HIGH to Beginning
of Reset
Chip Select LOW to Beginning of
Reset
Reset Pulse Width
Chip Select Hold After End of
Reset
Write Enable Hold After End of
Reset
Address Hold After End of Reset
Reset HIGH to Output in Low Z
[6]
Reset LOW to Output in
High Z
[6,7]
WRITE CYCLE
[8]
20
RESET CYCLE
20
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZ
is less than t
LZ
for any given device.
7. t
HZCS
, t
HZOE
, t
HZR
, and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
Document #: 38-05024 Rev. *A
Page 3 of 11
CY7C150
Switching Waveforms
Read Cycle No.1
[9,10]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C150-5
Read Cycle No. 2
CE
[9,11]
t
RC
t
ACS
OE
t
DOE
DATA OUT
t
LZOE
HIGH IMPEDANCE
t
LZCS
C150-6
t
HZOE
t
HZCS
DATA VALID
HIGH
IMPEDANCE
Write CycleNo.1 (WE Controlled)
[8]
t
WC
ADDRESS
t
SCS
CE
t
SA
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
t
LZWE
HIGH IMPEDANCE
t
HD
t
AW
t
PWE
t
HA
C150-7
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CS and OE = V
IL
.
11. Address prior to or coincident with CS transition LOW.
Document #: 38-05024 Rev. *A
Page 4 of 11
CY7C150
Switching Waveforms
(continued)
Write Cycle No. (CS Controlled)
2
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
C150-8
[8,12]
t
WC
t
SCS
t
HA
t
HD
Reset Cycle
[13]
t
RRC
ADDRESS
t
SAR
WE
t
SWER
t
HAR
t
HWER
CS
t
SCSR
t
PRS
t
HCSR
RESET
t
HZRS
DATA I/O
HIGH
IMPEDANCE
t
LZRS
OUTPUT VALID ZERO
C150-9
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
