CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined Sync SRAM
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Features
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Functional Description
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
SRAM integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE
1
), depth-expansion
Chip Enables (CE
2
and CE
3
), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BW
X
, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
Addresses and chip enables are registered at the rising edge of
the clock when either address strobe processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses may be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see sections
Pin Definitions on page 8
and
Truth
Table on page 11
for further details). Write cycles can be one to
two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
operates from a +3.3 V core power supply while all outputs may
operate with either a +2.5 or +3.3 V supply. All inputs and outputs
are JEDEC standard JESD8-5 compatible. For best practices
recommendations, refer to the Cypress application note
AN1064
“SRAM System Guidelines”.
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V/3.3 V I/O operation
Fast clock-to-output times
❐
3.0 ns (for 250 MHz device)
Provide high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1480BV33, CY7C1482BV33 available in JEDEC-
standard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free
and non Pb-free 165-ball fine-pitch ball grid array (FBGA)
package. CY7C1486BV33 available in Pb-free and
non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
3.0
500
120
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-15145 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 30, 2011
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Logic Block Diagram – CY7C1480BV33 (2 M × 36)
A 0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1482BV33 (4 M × 18)
ADDRESS
REGISTER
2
A[1:0]
A0, A1, A
MODE
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
WRITE REGISTER
DQ
B,
DQP
B
WRITE DRIVER
MEMORY
ARRAY
BW
A
BWE
GW
CE
1
CE2
CE3
OE
ENABLE
REGISTER
DQ
A,
DQP
A
WRITE REGISTER
DQ
A,
DQP
A
WRITE DRIVER
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
A
DQP
B
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 001-15145 Rev. *F
Page 2 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Logic Block Diagram – CY7C1486BV33 (1 M × 72)
A 0, A1,A
ADDRESS
REGISTER
A[1:0]
MODE
ADV
CLK
Q1
BINARY
COUNTER
CLR
Q0
ADSC
ADSP
BW
H
DQ
H
, DQP
H
WRITE DRIVER
DQ
F
, DQP
F
WRITE DRIVER
DQ
F
, DQP
F
WRITE DRIVER
DQ
E
, DQP
E
WRITE DRIVER
DQ
D
, DQP
D
WRITE DRIVER
DQ
H
, DQP
H
WRITE DRIVER
DQ
G
, DQP
G
WRITE DRIVER
DQ
F
, DQP
F
WRITE DRIVER
DQ
E
, DQP
E
BYTE
“a”
WRITE DRIVER
DQ
D
, DQP
D
WRITE DRIVER
DQ
C
, DQP
C
WRITE DRIVER
SENSE
AMPS
BW
G
BW
F
BW
E
MEMORY
ARRAY
BW
D
BW
C
DQ
C
, DQP
C
WRITE DRIVER
OUTPUT
REGISTERS
BW
B
DQ
B
, DQP
B
WRITE DRIVER
DQ
B
, DQP
B
WRITE DRIVER
DQ
A
, DQP
A
WRITE DRIVER
OUTPUT
BUFFERS
E
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
, DQP
A
WRITE DRIVER
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQP
A
DQP
B
DQP
C
DQP
D
DQP
E
DQP
F
DQP
G
DQP
H
ZZ
SLEEP
CONTROL
Document Number: 001-15145 Rev. *F
Page 3 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................. 10
Burst Sequences ....................................................... 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................. 10
Linear Burst Address Table (MODE = GND) ................ 10
ZZ Mode Electrical Characteristics ............................... 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
3.3-V TAP AC Test Conditions ...................................... 17
3.3-V TAP AC Output Load Equivalent ......................... 17
2.5-V TAP AC Test Conditions ...................................... 17
2.5-V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
TAP AC Switching Characteristics ............................... 18
TAP Timing ...................................................................... 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Exit Order (2 M × 36) ........................... 20
Boundary Scan Exit Order (4 M × 18) ........................... 20
Boundary Scan Exit Order (1 M × 72) ........................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Electrical Characteristics ............................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Reference Information ................................................... 34
Acronyms .................................................................. 34
Document Conventions ............................................. 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC Solutions ......................................................... 36
Document Number: 001-15145 Rev. *F
Page 4 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Configurations
Figure 1. CY7C1480BV33 100-pin TQFP Pinout
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 2. CY7C1482BV33 100-pin TQFP Pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQP
C
DQ
C
DQc
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1480BV33
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1482BV33
(4 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
A
A
V
SS
V
DD
MODE
A
A
A
A
A
1
A
0
A
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
Document Number: 001-15145 Rev. *F
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 5 of 36
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