CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture
Features
■
■
Functional Description
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined
burst SRAMs with No Bus Latency™ (NoBL logic,
respectively. They are designed to support unlimited true
back-to-back read or write operations with no wait states. The
CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are
equipped with the advanced (NoBL) logic required to enable
consecutive read or write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent read or write
transitions. The CY7C1470BV25, CY7C1472BV25, and
CY7C1474BV25 are pin-compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BW
a
–BW
d
for
CY7C1470BV25,
BW
a
–BW
b
for
CY7C1472BV25, and BW
a
–BW
h
for CY7C1474BV25) and a
Write Enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT™
Supports 250 MHz bus operations with zero wait states
❐
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
Single 2.5 V power supply
2.5 V IO supply (V
DDQ
)
Fast clock-to-output times
❐
3.0 ns (for 250-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1470BV25,
CY7C1472BV25
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV25
available in Pb-free and non-Pb-free 209-ball FBGA package
IEEE 1149.1 JTAG Boundary Scan compatible
Burst capability—linear or interleaved burst order
“ZZ” Sleep Mode option and Stop Clock option
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
3.0
450
120
200 MHz
3.0
450
120
167 MHz
3.4
400
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-15032 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 17, 2011
[+] Feedback
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Logic Block Diagram – CY7C1470BV25 (2 M × 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQ s
DQ P
a
DQ P
b
DQ P
c
DQ P
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1472BV25 (4 M × 18)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQ s
DQ P
a
DQ P
b
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 001-15032 Rev. *I
Page 2 of 29
[+] Feedback
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Logic Block Diagram – CY7C1474BV25 (1 M × 72)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
E
DQ s
DQ P
a
DQ P
b
DQ P
c
DQ P
d
DQ P
e
DQ P
f
DQ P
g
DQ P
h
WE
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 001-15032 Rev. *I
Page 3 of 29
[+] Feedback
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 8
Single Read Accesses ................................................ 8
Burst Read Accesses .................................................. 8
Single Write Accesses ................................................. 8
Burst Write Accesses .................................................. 9
Sleep Mode ................................................................. 9
Linear Burst Address Table (MODE = GND) .................. 9
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................... 9
ZZ Mode Electrical Characteristics ................................. 9
Truth Table ...................................................................... 10
Partial Write Cycle Description ..................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
TAP Controller State Diagram ....................................... 12
Test Access Port (TAP) ............................................. 12
TAP Controller Block Diagram ...................................... 12
Performing a TAP RESET ......................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 13
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 16
Identification Codes ....................................................... 17
Boundary Scan Exit Order (2 M × 36) ........................... 17
Boundary Scan Exit Order (4 M × 18) ........................... 18
Boundary Scan Exit Order (1 M × 72) ........................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Document Number: 001-15032 Rev. *I
Page 4 of 29
[+] Feedback
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Pin Configurations
Figure 1. 100-pin TQFP Pinout
A
A
CE
1
CE
2
BWd
BWc
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CE
1
CE
2
NC
NC
BWb
BWa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPb
DQb
DQb
V
DDQ
V
SS
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1470BV25
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
DQb
DQb
NC
V
SS
V
DD
NC
NC
V
DD
V
SS
ZZ
DQb
DQa
DQa
DQb
V
DDQ
V
DDQ
V
SS
V
SS
DQa
DQb
DQa
DQb
DQa DQPb
DQa
NC
V
SS
V
SS
V
DDQ
V
DDQ
NC
DQa
DQa
NC
DQPa
NC
CY7C1472BV25
(4 M × 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
NC(288)
NC(144)
MODE
A
A
A
A
A
1
A
0
V
SS
V
DD
NC(288)
NC(144)
A
A
A
A
A
A
A
A
A
Document Number: 001-15032 Rev. *I
V
SS
V
DD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 5 of 29
[+] Feedback
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
