CY7C1355C, CY7C1357C
9-Mbit (256 K × 36 / 512 K × 18) Flow-through
SRAM with NoBL™ Architecture
9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1355C/CY7C1357C
[1]
is a 3.3 V, 256 K × 36 /
512 K × 18 synchronous flow-through burst SRAM designed
specifically to support unlimited true back-to-back read/write
operations without the insertion of wait states. The
CY7C1355C/CY7C1357C is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BW
X
) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Can support up to 133-MHz bus operations with zero wait
states
❐
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Registered inputs for flow-through operation
Byte write capability
3.3 V / 2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in JEDEC-standard and Pb-free 100-pin TQFP,
Pb-free and non Pb-free 119-ball BGA package and 165-ball
FBGA package
Three chip enables for simple depth expansion.
Automatic power-down feature available using ZZ mode or CE
deselect
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability—linear or interleaved burst order
Low standby power
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Note
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05539 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 1, 2011
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CY7C1355C, CY7C1357C
Contents
Selection Guide ................................................................ 5
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 9
Functional Overview ...................................................... 10
Single Read Accesses .............................................. 10
Burst Read Accesses ................................................ 10
Single Write Accesses ............................................... 10
Burst Write Accesses ................................................ 11
Sleep Mode ............................................................... 11
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................. 11
Linear Burst Address Table (MODE = GND) ................ 11
ZZ Mode Electrical Characteristics ............................... 11
Truth Table ...................................................................... 12
Partial Truth Table for Read/Write ................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
TAP Controller State Diagram ....................................... 13
Test Access Port (TAP) ............................................. 13
TAP Controller Block Diagram ...................................... 13
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 14
TAP Timing ...................................................................... 15
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 16
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
119-ball BGA Boundary Scan Order ............................. 18
165-ball FBGA Boundary Scan Order ........................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read/Write Waveforms ............................................. 23
NOP, STALL and DESELECT Cycles ....................... 24
ZZ Mode Timing ........................................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Package Diagrams ........................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
Document Number: 38-05539 Rev. *H
Page 4 of 32
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