CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
FLEx18™ 3.3V 64K/128K x 36 and
128K/256K x 18 Synchronous Dual-Port RAM
Features
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Functional Description
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,
and 9 Mbit pipelined, synchronous, true dual port static RAMs
that are high speed, low power 3.3V CMOS. Two ports are
provided, permitting independent, simultaneous access to any
location in memory. The result of writing to the same location by
more than one port at the same time is undefined. Registers on
control, address, and data lines allow for minimal setup and hold
time.
During a Read operation, data is registered for decreased cycle
time. Each port contains a burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally (more
details to follow). The internal Write pulse width is independent
of the duration of the R/W input signal. The internal Write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down
the internal circuitry to reduce the static power consumption. One
cycle with chip enables asserted is required to reactivate the
outputs.
Additional features include: readback of burst-counter internal
address value on address lines, counter-mask registers to
control the counter wrap around, counter interrupt (CNTINT)
flags, readback of mask register value on address lines,
retransmit functionality, interrupt flags for message passing,
JTAG for boundary scan, and asynchronous Master Reset
(MRST).
The CY7C0833AV device in this family has limited features. See
Address Counter and Mask Register Operations
[16]
on page 6
for details.
True Dual-Ported Memory Cells that Allow Simultaneous
Access of the Same Memory Location
Synchronous Pipelined Operation
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices
Pipelined Output Mode Allows Fast Operation
0.18 micron CMOS for Optimum Speed and Power
High Speed Clock to Data Access
3.3V Low Power
❐
Active as Low as 225 mA (typ)
❐
Standby as Low as 55 mA (typ)
Mailbox Function for Message Passing
Global Master Reset
Separate Byte Enables on Both Ports
Commercial and Industrial Temperature Ranges
IEEE 1149.1 Compatible JTAG Boundary Scan
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)
120 TQFP (14 mm x 14 mm x 1.4 mm)
Pb-Free Packages Available
Counter Wrap Around Control
❐
Internal Mask Register Controls Counter Wrap Around
❐
Counter-Interrupt Flags to Indicate Wrap Around
❐
Memory Block Retransmit Operation
Counter Readback on Address Lines
Mask Register Readback on Address Lines
Dual Chip Enables on Both Ports for Easy Depth Expansion
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Table 1. Product Selection Guide
Density
Part Number
Maximum Speed (MHz)
Maximum Access Time -
Clock to Data (ns)
Typical Operating
Current (mA)
Package
512 Kbit
(32K x 18)
CY7C0837AV
167
4.0
225
144 FBGA
1 Mbit
(64K x 18)
CY7C0830AV
167
4.0
225
120 TQFP
144 FBGA
2 Mbit
(128K x 18)
CY7C0831AV
167
4.0
225
120 TQFP
144 FBGA
167
4.0
225
120 TQFP
144 FBGA
4 Mbit
(256K x 18)
CY7C0832AV
CY7C0832BV
[1]
133
4.4
225
120 TQFP
9 Mbit
(512K x 18)
CY7C0833AV
133
4.7
270
144 FBGA
Note
1. CY7C0832AV and CY7C0832BV are functionally identical.
Cypress Semiconductor Corporation
Document #: 38-06059 Rev. *S
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 03, 2009
[+] Feedback
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Configurations
Figure 1. 144-Ball BGA (Top View)
CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV
1
2
3
4
5
6
7
8
9
10
11
12
A
DQ17
L
DQ16
L
DQ14
L
DQ12
L
DQ10
L
DQ9
L
DQ9
R
DQ10
R
DQ12
R
DQ14
R
DQ16
R
DQ17
R
B
A0
L
A1
L
DQ15
L
DQ13
L
DQ11
L
MRST
NC
DQ11
R
DQ13
R
DQ15
R
A1
R
A0
R
C
A2
L
A3
L
CE1
L
[7]
INT
L
CNTINT
L
[9]
ADS
L
[8]
ADS
R
[8]
CNTINT
R
[9]
INT
R
CE1
R
[7]
A3
R
A2
R
D
A4
L
A5
L
CE0
L
[8]
NC
VDD
VDD
VDD
VDD
NC
CE0
R
[8]
A5
R
A4
R
E
A6
L
A7
L
B1
L
NC
VDD
VSS
VSS
VDD
NC
B1
R
A7
R
A6
R
F
A8
L
A9
L
C
L
NC
VSS
VSS
VSS
VSS
NC
C
R
A9
R
A8
R
G
A10
L
A11
L
B0
L
NC
VSS
VSS
VSS
VSS
NC
B0
R
A11
R
A10
R
H
A12
L
A13
L
OE
L
NC
VDD
VSS
VSS
VDD
NC
OE
R
A13
R
A12
R
J
A14
L
A15
L
[3]
RW
L
NC
VDD
VDD
VDD
VDD
NC
RW
R
A15
R
[3]
A14
R
K
A16
L
[4]
A17
L
[5]
CNT/MSK
L
[7]
TDO
CNTRST
L
[7]
TCK
TMS
CNTRST
R
[7]
TDI
CNT/MSK
R
[7]
A17
R
[5]
A16
R
[4]
L
A18
L
[6]
NC
DQ6
L
DQ4
L
DQ2
L
CNTEN
L
[8]
CNTEN
R
[8]
DQ2
R
DQ4
R
DQ6
R
NC
A18
R
[6]
M
DQ8
L
DQ7
L
DQ5
L
DQ3
L
DQ1
L
DQ0
L
DQ0
R
DQ1
R
DQ3
R
DQ5
R
DQ7
R
DQ8
R
Notes
3. Leave this ball unconnected for CY7C0837AV.
4. Leave this ball unconnected for CY7C0837AV and CY7C0830AV.
5. Leave this ball unconnected for CY7C0837AV, CY7C0830AV and CY7C0831AV.
6. Leave this ball unconnected for CY7C0837AV, CY7C0830AV, CY7C0831AV, and CY7C0832AV.
7. These balls are not applicable for CY7C0833AV device. They must be tied to VDD.
8. These balls are not applicable for CY7C0833AV device. They must be tied to VSS.
9. These balls are not applicable for CY7C0833AV device. They must not be connected.
Document #: 38-06059 Rev. *S
Page 3 of 28
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CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Pin Definitions
Left Port
A
0L
–A
18L[2]
ADS
L[8]
Right Port
A
0R
–A
18R[2]
ADS
R[8]
Address Inputs.
Address Strobe Input.
Used as an address qualifier. This signal should be asserted LOW for
the part using the externally supplied address on the address pins and for loading this address
into the burst address counter.
Active LOW Chip Enable Input.
Active HIGH Chip Enable Input.
Clock Signal.
Maximum clock input rate is f
MAX
.
Counter Enable Input.
Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are
asserted LOW.
Counter Reset Input.
Asserting this signal LOW resets to zero the unmasked portion of the
burst address counter of its respective port. CNTRST is not disabled by asserting ADS or
CNTEN.
Address Counter Mask Register Enable Input.
Asserting this signal LOW enables access to
the mask register. When tied HIGH, the mask register is not accessible and the address counter
operations are enabled based on the status of the counter control signals.
Data Bus Input/Output.
Output Enable Input.
This asynchronous signal must be asserted LOW to enable the DQ data
pins during Read operations.
Mailbox Interrupt Flag Output.
The mailbox permits communications between ports. The
upper two memory locations are used for message passing. INT
L
is asserted LOW when the
right port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is
deasserted HIGH when it reads the contents of its mailbox.
Counter Interrupt Output.
This pin is asserted LOW when the unmasked portion of the counter
is incremented to all ‘1s.’
Read/Write Enable Input.
Assert this pin LOW to write to, or HIGH to Read from the dual port
memory array.
Byte Select Inputs.
Asserting these signals enables Read and Write operations to the corre-
sponding bytes of the memory array.
Master Reset Input.
MRST is an asynchronous input signal and affects both ports. Asserting
MRST LOW performs all of the reset functions as described in the text. A MRST operation is
required at power up.
JTAG Test Mode Select Input.
It controls the advance of JTAG TAP state machine. State
machine transitions occur on the rising edge of TCK.
JTAG Test Data Input.
Data on the TDI input is shifted serially into selected registers.
JTAG Test Clock Input.
JTAG Test Data Output.
TDO transitions occur on the falling edge of TCK. TDO is normally
three-stated except when captured data is shifted out of the JTAG TAP.
Ground Inputs.
Power Inputs.
Description
CE0
L[8]
CE1
L[7]
CLK
L
CNTEN
L[8]
CE0
R[8]
CE1
R[7]
CLK
R
CNTEN
R[8]
CNTRST
L[7]
CNT/MSK
L[7]
CNTRST
R[7]
CNT/MSK
R[7]
DQ
0L
–DQ
17L
OE
L
INTL
DQ
0R
–DQ
17R
OE
R
INTR
CNTINT
L[9]
R/W
L
B
0L
–B
1L
CNTINT
R[9]
R/W
R
B
0R
–B
1R
MRST
TMS
TDI
TCK
TDO
V
SS
V
DD
Byte Select Operation
Control Pin
B
0
B
1
Effect
DQ
0–8
Byte Control
DQ
9–17
Byte Control
Document #: 38-06059 Rev. *S
Page 5 of 28
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