CY7C056V CY7C057V CY7C037V CY7C038V3.3 V 16K/32K × 36 FLEx36™
Asynchronous Dual-Port Static RAM
CY7C056V
CY7C057V
3.3 V 16K/32K × 36 FLEx36™
Asynchronous Dual-Port Static RAM
3.3 V 16K/32K × 36 FLEx36™ Asynchronous Dual-Port Static RAM
Features
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Pb-free packages available
Compact packages:
❐
144-pin TQFP (20 × 20 × 1.4 mm)
❐
172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)
True dual-ported memory cells that allow simultaneous access
of the same memory location
16K × 36 organization (CY7C056V)
32K × 36 organization (CY7C057V)
0.25-micron Complimentary metal oxide semiconductor
(CMOS) for optimum speed/power
High-speed access: 12/15 ns
Low operating power
❐
Active: I
CC
= 250 mA (typical)
❐
Standby: I
SB3
= 10
A
(typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 72 bits or more using Master/Slave
Chip Select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Byte select on left port
Bus matching on right port
Depth expansion via dual chip enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 144-pin thin quad plastic flatpack (TQFP) or
172-ball ball grid array (BGA)
Functional Description
The CY7C056V and CY7C057V are low-power CMOS 16K and
32K × 36 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 36-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 72-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 72-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE)
[1]
,
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a
mailbox. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in use.
The semaphore logic is comprised of eight shared latches. Only
one side can control the latch (semaphore) at any time. Control
of a semaphore indicates that a shared resource is in use. An
automatic Power-down feature is controlled independently on
each port by Chip Select (CE
0
and CE
1
) pins.
The CY7C056V and CY7C057V are available in 144-pin TQFP
and 172-ball BGA packages.
For a complete list of related resources,
click here.
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Selection Guide
Description
Maximum access time
Typical operating current
Typical standby current for I
SB1
(Both ports TTL level)
Typical standby current for I
SB3
(Both ports CMOS level)
CY7C056V
CY7C057V
-12
12
250
55
10
CY7C056V
CY7C057V
-15
15
240
50
10
Unit
ns
mA
mA
A
Note
1. CE is LOW when CE
0
V
IL
and CE
1
V
IH
.
Cypress Semiconductor Corporation
Document Number: 38-06055 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 27, 2017
CY7C056V
CY7C057V
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Architecture ...................................................................... 7
Functional Overview ........................................................ 7
Write Operation ........................................................... 7
Read Operation ........................................................... 7
Interrupts ..................................................................... 8
Busy ............................................................................ 8
Master/Slave ............................................................... 8
Semaphore Operation ................................................. 9
Bus Match Operation ................................................. 11
Maximum Ratings ........................................................... 12
Operating Range ............................................................. 12
Electrical Characteristics ............................................... 12
Capacitance .................................................................... 13
AC Test Loads and Waveforms ..................................... 13
Data Retention Mode ...................................................... 14
Timing .............................................................................. 14
Switching Characteristics .............................................. 15
Switching Waveforms .................................................... 17
Ordering Information ...................................................... 23
16K × 36 3.3 V Asynchronous Dual Port SRAM ....... 23
32K × 36 3.3 V Asynchronous Dual Port SRAM ....... 23
Ordering Code Definitions ......................................... 23
Package Diagrams .......................................................... 24
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Errata ............................................................................... 27
Part Numbers Affected .............................................. 27
Qualification Status ................................................... 27
Errata Summary ........................................................ 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC®Solutions ....................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
Document Number: 38-06055 Rev. *L
Page 3 of 29
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