CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Fully asynchronous operation
Automatic power down
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
On chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT flag for port-to-port communication
Separate upper byte and lower byte control
Pin select for Master or Slave (M/S)
Commercial and industrial temperature ranges
Available in 100-pin Pb-free TQFP and 100-pin TQFP
True dual-ported memory cells which enable simultaneous
access of the same memory location
4, 8 or 16K × 16 organization
(CY7C024AV/024BV
[1]
/ 025AV/026AV)
4 or 8K × 18 organization (CY7C0241AV/0251AV)
16K × 18 organization (CY7C036AV)
0.35 micron CMOS for optimum speed and power
High speed access: 20 and 25 ns
Low operating power
❐
Active: I
CC
= 115 mA (typical)
❐
Standby: I
SB3
= 10
A
(typical)
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
L
LB
L
OE
L
8/9
8/9
8/9
CE
R
LB
R
OE
R
[2]
IO
8/9L
–IO
15/17L
[3]
IO
0L
–IO
7/8L
[2]
IO
Control
IO
Control
8/9
IO
8/9L
–IO
15/17R
IO
0L
–IO
7/8R
[3]
A
0L
–A
11/1213L
[4]
[4]
12/13/14
Address
Decode
12/13/14
True Dual-Ported
RAM Array
Address
Decode
12/13/14
12/13/14
A
0R
–A
11/12/13R
[4]
[4]
A
0L
–A
11/12/13L
CE
L
OE
L
R/W
L
SEM
L
[5]
BUSY
L
INT
L
UB
L
LB
L
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO
8
–IO
15
for x16 devices; IO
9
–IO
17
for x18 devices.
3. IO
0
–IO
7
for x16 devices; IO
0
–IO
8
for x18 devices.
4. A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
A
0R
–A
11/12/13R
CE
R
OE
R
R/W
R
SEM
R
[5]
M/S
BUSY
R
INT
R
UB
R
LB
R
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 30, 2011
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CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
13L
IO
0L
–IO
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
Right Port
CE
R
R/W
R
OE
R
A
0R
–A
13R
IO
0R
–IO
17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
Chip Enable
Read and Write Enable
Output Enable
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K)
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO
8
–IO
15
for x16 devices; IO
9
–IO
17
for x18 devices)
Lower Byte Select (IO
0
–IO
7
for x16 devices; IO
0
–IO
8
for x18 devices)
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared latches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE) pin.
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP.
Description
Architecture
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY pin is provided on each port. Two Interrupt (INT)
pins can be used for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). They also have an
automatic power down feature controlled by CE. Each port has its
own output enable control (OE), which enables data to be read from
the device.
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of RW to guarantee a valid write. A write operation is controlled
by either the RW pin (see
Figure 8
on page 12) or the CE pin (see
Figure 9
on page 12). Required inputs for non-contention opera-
tions are summarized in
Table 1
on page 7.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the data
read is not deterministic. Data is valid on the port t
DDD
after the
data is presented on the other port.
Functional Description
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S pin is provided for implementing 32 or
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual port video and graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
Document #: 38-06052 Rev. *M
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available t
ACE
after CE or t
DOE
after OE is
asserted. If the user wants to access a semaphore flag, then the
SEM pin and OE must be asserted.
Interrupts
The upper two memory locations are for message passing. The
highest
memory
location
(FFF
for
the
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Page 5 of 20
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