• Available in a Pb-free and non Pb-free standard 28-pin
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1
and 28-pin DIP packages
Functional Description
[1]
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and Tri-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
A
14
A
13
A
12
A
11
A
1
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
32K × 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 3, 2006
[+] Feedback
CY62256
Product Portfolio
Power Dissipation
V
CC
Range (V)
Product
CY62256L
CY62256LL
CY62256LL
CY62256LL
Com’l/Ind’l
Commercial
Industrial
Automotive
Min.
4.5
Typ.
[2]
5.0
Max.
5.5
Operating, I
CC
(mA)
Speed
(ns)
55/70
70
55/70
55
Typ.
[2]
25
25
25
25
Max.
50
50
50
50
Standby, I
SB2
(µA)
Typ.
[2]
2
0.1
0.1
0.1
Max.
50
5
10
15
Pin Configurations
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Narrow SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A
4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
DIP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A
4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
V
CC
WE
A
4
A
3
A
2
A
1
OE
7
6
5
4
3
2
1
28
27
26
25
24
23
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TSOP I
Reverse Pinout
Top View
(not to scale)
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
0
Pin Definitions
Pin Number
1–10, 21, 23–26
11–13, 15–19,
27
20
22
Type
Input
Input/Output
Input/Control
Input/Control
Input/Control
A
0
–A
14
. Address Inputs
I/O
0
–/O
7
. Data lines. Used as input or output lines depending on operation
WE.
When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
CE.
When LOW, selects the chip. When HIGH, deselects the chip
OE.
Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input
data pins
GND.
Ground for the device
Description
14
28
Ground
Power Supply
V
CC
. Power supply for the device
Note:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25°C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 38-05248 Rev. *F
Page 2 of 14
[+] Feedback
CY62256
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .............................................. –0.5V to +7V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[3]
................................ –0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Automotive
Ambient Temperature (T
A
)
[4]
0
°
C to +70
°
C
–40
°
C to +85
°
C
–40
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
CY62256−55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
V
CC
= 5.5V,
I
OUT
= 0 mA,
f = f
Max
= 1/t
RC
L
LL
L
LL
L
LL - Com’l
LL - Ind’l
LL - Auto
Output Leakage Current GND < V
O
< V
CC
, Output Disabled
Test Conditions
V
CC
= Min., I
OH
=
−1.0
mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
–0.5
–0.5
–0.5
25
25
0.4
0.3
2
0.1
0.1
0.1
Min. Typ.
[2]
2.4
0.4
V
CC
+0.5V
0.8
+0.5
+0.5
50
50
0.6
0.5
50
5
10
15
2.2
–0.5
–0.5
–0.5
25
25
0.4
0.3
2
0.1
0.1
Max.
2.4
0.4
V
CC
+0.5V
0.8
+0.5
+0.5
50
50
0.6
0.5
50
5
10
µA
mA
CY62256−70
Min. Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
Automatic CE
V
CC
= 5.5V, CE > V
IH
,
Power-down Current— V
IN
> V
IH
or V
IN
< V
IL
,
TTL Inputs
f = f
Max
V
CC
= 5.5V,
Automatic CE
Power-down Current— CE > V
CC
−
0.3V
CMOS Inputs
V
IN
> V
CC
−
0.3V, or
V
IN
< 0.3V, f = 0
I
SB2
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz, V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
[5]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch,
2-layer printed circuit board
DIP
75.61
43.12
SOIC
76.56
36.07
TSOP
93.89
24.64
RTSOP
93.89
24.64
Unit
°C/W
°C/W
Notes:
3. V
IL
(min.) =
−
2.0V for pulse durations of less than 20 ns.
4. T
A
is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05248 Rev. *F
Page 3 of 14
[+] Feedback
CY62256
AC Test Loads and Waveforms
R1 1800Ω
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
5 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
990Ω
GND
< 5 ns
5V
OUTPUT
3.0V
10%
R1 1800Ω
ALL INPUT PULSES
90%
90%
10%
< 5 ns
(a)
(b)
THEVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Data Retention Characteristics
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
L
LL - Com’l
LL - Ind’l
LL - Auto
t
CDR[5]
t
R[5]
Chip Deselect to Data Retention Time
Operation Recovery Time
0
t
RC
V
CC
= 2.0V, CE > V
CC
−
0.3V,
V
IN
> V
CC
−
0.3V, or V
IN
< 0.3V
Conditions
[6]
Min.
2.0
2
0.1
0.1
0.1
50
5
10
10
Typ.
[2]
Max.
Unit
V
µA
µA
µA
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
>
2V
V
CC(min)
t
R
CE
Note:
6. No input may exceed V
CC
+ 0.5V.
Document #: 38-05248 Rev. *F
Page 4 of 14
[+] Feedback
CY62256
Switching Characteristics
Over the Operating Range
[7]
CY62256−55
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[8, 9]
WE HIGH to Low-Z
[8]
5
55
45
45
0
0
40
25
0
20
5
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[8]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
0
55
5
20
0
70
5
20
5
25
5
55
25
5
25
55
55
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
CY62256−70
Min.
Max.
Unit
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100 pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
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