CY62146E MoBL
4-Mbit (256K x 16) Static RAM
Features
■
■
■
Very high speed: 45 ns
Wide voltage range: 4.5 V to 5.5 V
Ultra low standby power
❐
Typical standby current: 1
A
❐
Maximum standby current: 7
A
Ultra low active power
❐
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 44-pin thin small outline package (TSOP)
II package
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O
0
through
I/O
15
) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
) is written into the location
specified on the address pins (A
0
through A
17
). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
17
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O
0
to I/O
7
. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See
Table
for a complete description
of read and write modes.
■
■
■
■
■
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life (MoBL
) in portable
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
A
11
A
12
A
13
A
15
A
14
A
16
A
17
Cypress Semiconductor Corporation
Document Number: 001-07970 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 29, 2011
CY62146E MoBL
Contents
Features ............................................................................. 1
Functional Description ..................................................... 1
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
Data Retention Characteristics ....................................... 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Document Number: 001-07970 Rev. *H
Page 2 of 14
CY62146E MoBL
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View)
[1]
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
17
A
16
A
15
A
14
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
8
A
9
A
10
A
11
A
12
Product Portfolio
Power Dissipation
Product
Range
Min
CY62146ELL
Ind’l/Auto-A
4.5
V
CC
Range (V)
Speed
(ns)
Max
5.5
45
Operating I
CC
, (mA)
f = 1 MHz
Typ
[2]
2
Max
2.5
f = f
max
Typ
[2]
15
Max
20
Standby, I
SB2
(A)
Typ
[2]
1
Max
7
Typ
[2]
5.0
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
Document Number: 001-07970 Rev. *H
Page 3 of 14
CY62146E MoBL
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground potential .................–0.5 V to 6.0 V
DC voltage applied to outputs
in high Z state
[3, 4]
...........................................–0.5 V to 6.0 V
DC input voltage
[3, 4]
.......................................–0.5 V to 6.0 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage............................................ >2001 V
(MIL-STD-883, Method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Device
CY62146ELL
Range
Industrial/
Auto-A
Ambient
Temperature
V
CC
[5]
–40 °C to +85 °C 4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB2
[7]
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
V
CC
operating supply
current
I
OH
= –1.0 mA
I
OL
= 2.1 mA
4.5 < V
CC
< 5.5
4.5 < V
CC
< 5.5
GND < V
I
< V
CC
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CCmax
I
OUT
= 0 mA, CMOS levels
Test Conditions
Min
2.4
–
2.2
–0.5
–1
–1
–
–
–
Typ
[6]
–
–
–
–
–
–
15
2
1
Max
–
0.4
V
CC
+ 0.5
0.8
+1
+1
20
2.5
7
A
Unit
V
V
V
V
A
A
mA
Output leakage current GND < V
O
< V
CC
, output disabled
Automatic CE power
CE > V
CC
– 0.2 V, V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
down current — CMOS f = 0, V
CC
= V
CC(max)
inputs
Capacitance
Parameter
[8]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Thermal Resistance
Parameter
[8]
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two layer
printed circuit board
TSOP II
77
13
Unit
C/W
C/W
Notes
3. V
IL
(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH
(max) = V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full Device AC operation assumes a minimum of 100
s
ramp time from 0 to V
CC
(min) and 200
s
wait time after V
CC
stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
7. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs are left floating.
8. Tested initially after any design or process changes that may affect these parameters.
Document Number: 001-07970 Rev. *H
Page 4 of 14
CY62146E MoBL
Figure 2. AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
V
CC
10%
GND
R2 Rise Time = 1 V/ns
Equivalent to:
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Unit
V
Parameters
R1
R2
R
TH
V
TH
5.0 V
1800
990
639
1.77
Data Retention Characteristics
Over the Operating Range
Parameter
V
DR
I
CCDR
[10]
t
CDR
[11]
t
R
[12]
Description
V
CC
for data retention
Data retention current
Chip deselect to data
retention time
Operation recovery time
Figure 3. Data Retention Waveform
V
CC
= 2 V, CE > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V
Conditions
Min
2
–
0
45
Typ
[9]
–
1
–
–
Max
–
7
–
–
Unit
V
A
ns
ns
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 2.0 V
V
CC(min)
t
R
CE
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
10. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
SB2
/ I
CCDR
spec. Other inputs are left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
s
or stable at V
CC(min)
> 100
s.
Document Number: 001-07970 Rev. *H
Page 5 of 14
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