Latch up Current..................................................... > 200 mA
Operating Range
Device
CY62128ELL
Range
Ind’l/Auto-A
Auto-E
Ambient
Temperature
–40°C to +85°C
–40°C to +125°C
V
CC
[7]
4.5V to 5.5V
Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB2 [8]
Description
Output HIGH
Voltage
Output LOW
Voltage
Test Conditions
I
OH
= –1 mA
I
OL
= 2.1 mA
2.2
–0.5
–1
–1
11
1.3
1
45 ns (Ind’l/Auto-A)
Min
2.4
0.4
V
CC
+ 0.5
0.8
+1
+1
16
2
4
2.2
–0.5
–4
–4
11
1.3
1
Typ
[3]
55 ns (Auto-E)
Min
2.4
0.4
V
CC
+ 0.5
0.8
+4
+4
35
4
30
Typ
[3]
Max
Max
Unit
V
V
V
V
μA
μA
mA
Input HIGH Voltage V
CC
= 4.5V to 5.5V
Input LOW voltage V
CC
= 4.5V to 5.5V
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power down
Current—CMOS
Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
f = 1 MHz
CMOS levels
CE
1
> V
CC
– 0.2V or CE
2
< 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
f = 0, V
CC
= V
CC(max)
μA
Capacitance
(For all Packages)
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+ 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100
μs
ramp time from 0 to V
CC
(min) and 200
μs
wait time after V
CC
stabilization.
8. Only chip enables (CE
1
and CE
2
) must be at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05485 Rev. *F
Page 3 of 12
[+] Feedback
MoBL
®
CY62128E
Thermal Resistance
[9]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
SOIC
Package
48.67
25.86
STSOP
Package
32.56
3.59
TSOP
Package
33.01
3.42
Unit
°C/W
°C/W
AC Test Loads and Waveform
V
CC
OUTPUT
R1
3.0V
30 pF
INCLUDING
JIG AND
SCOPE
R2
GND
Rise Time = 1 V/ns
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THEVENIN
EQUIVALENT
OUTPUT
R
TH
V
Parameters
R1
R2
R
TH
V
TH
Value
1800
990
639
1.77
Unit
Ω
Ω
Ω
V
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR [8]
t
CDR [9]
t
R [10]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
V
CC
= V
DR
, CE
1
> V
CC
−
0.2V or CE
2
< 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Ind’l/Auto-A
Auto-E
0
t
RC
Conditions
Min
2
4
30
Typ
[3]
Max
Unit
V
μA
μA
ns
ns
Data Retention Waveform
[11]
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 2.0V
V
CC(min)
t
R
CE
Notes
10. Full device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
μs
or stable at V
CC(min)
> 100
μs.
11. CE is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
Document #: 38-05485 Rev. *F
Page 4 of 12
[+] Feedback
MoBL
®
CY62128E
Switching Characteristics
(Over the Operating Range)
[12]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z
[13, 14]
WE HIGH to Low-Z
[13]
10
45
35
35
0
0
35
25
0
18
10
55
40
40
0
0
40
25
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[13]
OE HIGH to High-Z
[13, 14]
CE
1
LOW and CE
2
HIGH to Low-Z
[13]
CE
1
HIGH or CE
2
LOW to High-Z
[13, 14]
CE
1
LOW and CE
2
HIGH to Power Up
CE
1
HIGH or CE
2
LOW to Power Down
0
45
10
18
0
55
5
18
10
20
10
45
22
5
20
45
45
10
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
45 ns (Ind’l/Auto-A)
Min
Max
55 ns (Auto-E)
Min
Max
Unit
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified I
OL
/I
OH
as shown in the
“”
on page 4.
13. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
14. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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