CY5057
High-Frequency Flash Programmable
PLL Die with Spread Spectrum
Features
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Benefits
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Flash programmable die for in-package programming of crystal
oscillators
High resolution phase-locked loop (PLL) with 10-bit multiplier
and 7-bit divider
Flash programmable capacitor tuning array
Simple 2-pin programming interface (excluding VDD and VSS
pins)
On-chip oscillator used with external 25.1 MHz fundamental
tuned crystal
Flash programmable spread spectrum with spread
percentages between +0.25% and +2.00%
Spread spectrum on/off function
Operating frequency
❐
5 to 170 MHz at 3.3V ± 10%
Seven-bit linear post divider with divide options from
divide-by-2 to divide-by-127
Programmable PD# or OE pin
Enables quick turnaround of custom oscillators and lowers
inventory costs through stocking blank parts. In addition, the
part may be Flash programmed up to 100 times. This reduces
programming errors and provides an easy upgrade path for
existing designs.
Enables synthesis of highly accurate and stable output clock
frequencies with zero or low PPM.
Enables fine tuning of output clock frequency by adjusting the
CLoad of the crystal.
Allows the device to go into standard 4 or 6-pin packages.
Lowers cost of oscillator, because PLL may be programmed to
a high frequency using a low frequency, low cost crystal.
Provides various spread percentage.
Provides the ability to enable or disable spread spectrum with
an external pin.
Provides flexibility in output configurations and testing.
Enables low operation or output enable function.
Provides flexibility for system applications through selectable
instantaneous or synchronous change in outputs.
Suitable for most PC, consumer, and networking applications.
Has lower EMI than oscillators.
Easy to use software support for design entry.
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Programmable asynchronous or synchronous OE and PD#
modes
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Low jitter output
❐
< 200 ps (pk-pk) at 3.3V ± 10%
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Controlled rise and fall times and output slew rate
Software configuration support
Logic Block Diagram
XIN
XOUT
Crystal Osc
with 8-bit
Cap Array
7-bit
÷Q
10-bit
÷P
Spread
Spectrum
100- to
400-MHz
PLL
7-bit
Output
Divider
Block
OUT
SSON#
PD#/OE
Flash Configuration/
Spread Spectrum Storage
Cypress Semiconductor Corporation
Document #: 38-07363 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 3, 2008
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CY5057
Die Pad Description
Note
Active die size: X = 75.0 mils / 1907
μm
Y = 56.2 mils / 1428
μm
Scribe: Y (horizontal) = 2.8 mils / 71
μm
X (vertical) = 3.4 mils / 86.2
μm
Bond pad opening: 85
μm
x 85
μm
Pad pitch: 125
μm
x 125
μm
(pad center to pad center)
Wafer thickness: 11 mils and 29 mils TYPICAL (See
Ordering Information table for details)
Die Pad Summary
[Pad coordinates are referenced from the center of the die (X = 0, Y = 0)]
Table 1. Die Pad Summary
Name
V
DD
V
SS
XIN
XOUT
PD#/OE
V
PP
SDA
SSON#
10
Die Pad
1,2
6,7
4
3
5
Power supply
Ground
Crystal gate pin
Crystal drain pin
Flash programmable to function as power down or output enable
in normal operating mode. Weak pull up is enabled by default
Super voltage when going into programming mode
Data pin when going into and when in programming mode
Active low spread spectrum control. Asserting LOW turns the
internal modulation waveform on. Strong pull down is enabled by
default. Pull down is disabled in power down mode
Clock pin in programming mode. Must be double bonded to the
OUT pad for pinouts not using the SSON# function. There is an
internal pull down resistor on this pad
9
Clock output. There is an internal pull down resistor on this pad.
Weak pull down is enabled by default. Default output is from the
reference
No connect pin (do not connect this pad)
834.183
462.840
834.183
589.848
Description
X Coordinate
–843.612
883.743, 887.355
–843.612
–843.612
–843.612
Y Coordinate
597.849, 427.266
–563.304, –369.957
–1.806
236.565
–424.662
SCL
OUT
NC
8
834.183
335.832
Document #: 38-07363 Rev. *E
Page 2 of 10
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CY5057
Functional Description
CY5057 is a Flash programmable, high accuracy, PLL-based die
designed for the crystal oscillator market. It also contains spread
spectrum circuitry that is enabled or disabled with an external
pin. The die is integrated with a low cost 25.1 MHz fundamental
tuned crystal in a 4 or 6-pin through hole or surface mount
package. The oscillator devices may be stocked as blank parts
and custom frequencies programmed in-package at the last
stage before shipping. This enables faster manufacturing of
custom and standard crystal oscillators without the need for
dedicated and expensive crystals.
CY5057 contains an on-chip oscillator and unique oscillator
tuning circuit for fine tuning the output frequency. The crystal
C
load
is selectively adjusted by programming a set of Flash
memory bits. This feature is used to compensate for crystal
variations or to obtain a more accurate synthesized frequency.
CY5057 uses a simple two-pin programming interface excluding
the V
SS
and V
DD
pins
.
Clock outputs are generated from 5 MHz
to 170 MHz at 3.3V ± 10% operating voltage. You can reprogram
the entire Flash configuration multiple times to alter or reuse the
programmed inventory.
CY5057 PLL die is designed for very high resolution. It has a
10-bit feedback counter multiplier and a 7-bit reference counter
divider. This enables the synthesis of highly accurate and stable
output clock frequencies with zero or low PPM error. The output
of the PLL or the oscillator is further modified by a 7-bit linear
post divider with a total of 126 divider options (2 to 127).
CY5057 also contains flexible power management controls.
These parts include both power down mode (PD# = 0) and
output enable mode (OE = 1). The power down and output
enable modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output signal.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enables CY5057 to have low
jitter and accurate outputs. This makes it suitable for most PC,
networking, and consumer applications.
CY5057 also has an additional spread spectrum feature that is
disabled or enabled with an external pin. See
Spread Spectrum
for details.
PLL Output Frequency
CY5057 contains a high resolution PLL with a 10-bit multiplier
and a 7-bit divider. The output frequency of the PLL is
determined by the following equation:
2
• (
P
BL
+ 4
)
+ Po
-
F
PLL
= ---------------------------------------------
•
F
REF
(
Q
L
+ 2
)
In this equation:
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Equation (1)
Q
L
is the loaded or programmed reference counter value
(Q counter)
P
BL
is the loaded or programmed feedback counter value
(P counter)
Po is the P offset bit (is only 0 or 1)
In spread spectrum mode, the time averaged P value is used to
calculate the average frequency.
Power Management Features
CY5057 contains Flash programmable PD# (active LOW) and
OE (active HIGH) functions. If power down mode is selected
(PD# = 0), the oscillator and PLL are placed in a low supply
current standby mode and the output is tri-stated and weakly
pulled low. The oscillator and PLL circuits must relock when the
part leaves power down mode. If output enable mode is selected
(OE = 0), the output is tri-stated and weakly pulled low. In this
mode, the oscillator and PLL circuits continue to operate allowing
a rapid return to normal operation when the output is enabled.
In addition, the PD# and OE modes may be programmed to
occur synchronously or asynchronously with respect to the
output signal. When the asynchronous setting is used, the power
down or output disable occurs immediately (allowing for logic
delays) irrespective of the position in the clock cycle. However,
when the synchronous setting is used, the part waits for a falling
edge at the output before power down or output enable signal
initiated, thus preventing output glitches. In asynchronous or
synchronous setting, the output is always enabled
synchronously by waiting for the next falling edge of the output.
Flash Configuration and Spread Spectrum
Storage Block
Table 2
summarizes the features configurable by the Flash
memory bits. Refer to “CY5057 Programming Specification” for
programming details. The specification can be obtained from
your Cypress factory representative.
Table 2. Flash Programmable Features
Feedback counter value (P)
Reference counter value (Q)
Output divider selection
Oscillator tuning (load capacitance values)
Oscillator direct output
Power management mode (OE or PD#)
Power management timing (synchronous or asynchronous)
Spread spectrum
Pull up and Pull down resistors
Document #: 38-07363 Rev. *E
Adjust
Frequency
Spread Spectrum
CY5057 contains spread spectrum with Flash programmable
spread percentage and modulation frequency. Center spread
nonlinear “hershey kiss” modulation is obtained. Spread
percentage is programmed to values between +0.250% and
+2.00%, in 0.25% intervals. Only one spread profile (for one
specific percentage spread and for one output frequency) may
be programmed into the device at a time.
CY5057 has a spread spectrum on and off function. The spread
spectrum is enabled or disabled through an external pin. Timing
this feature is explained in
Switching Waveforms
on page 7.
Page 3 of 10
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CY5057
Figure 1. Crystal Oscillator Tuning Circuit
RF
XIN
XOUT
C
XIN
C
XOUT
C7
C6
C5
C4
C3
C2
C1
C0
C0
C1
C2
C3
C4
C5
C6
C7
Table 3. Crystal Oscillator Tuning Cap Values
Bit
[1]
C
7
(MSB)
C
6
C
5
C
4
C
3
C
2
C
1
C
0
(LSB)
Capacitance per Bit (pF)
24.32
12.16
6.08
3.04
1.52
0.76
0.38
0.19
Inkless Die Pick Map (DPM) Format
Cypress ships inkless wafers to customers with an accompa-
nying die pick map, which is used to determine the good die for
assembly and programming. Customers can also access
individual DPM files at their convenience through
ftp.cypress.com
with a valid user account login and password.
Contact your local Cypress Field Application Engineer (FAE) or
sales representative for a customer FTP account. The DPM files
are named using the fab lot number and wafer number scribed
on the wafer. The DPM files are transferred to the customer’s
FTP account when the factory ships out the wafers against their
purchase order (PO).
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply voltage ................................................. –0.5 to +7.0V
Input voltage .............................................–0.5V to V
DD
+ 0.5
Storage temperature (non condensing) ...... –55°C to +125°C
Junction temperature................................. –40°C to +125°C
Data retention at Tj = 125°C..................................> 10 years
Maximum non volatile programming cycles......................100
Static discharge voltage........................................... > 2000V
(per MIL-STD-883, method 3015)
Output (pad 9) sink or sources current ........20 mA maximum
Note
1. C
XIN,
C
XOUT,
and parasitic capacitance due to fixture and package should be included when calculating the total capacitance.
Document #: 38-07363 Rev. *E
Page 4 of 10
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CY5057
Operating Conditions
Parameter
V
DD
T
AJ[2]
C
LC
X
REF
C
in
C
XIN
C
Xout
T
PSRT
Supply voltage (3.3V)
Operating temperature, junction
Maximum capacitive load on the output (CMOS levels spec)
V
DD
= 3.0V to 3.6V, output frequency = 5 MHz to 170 MHz
Reference frequency with spread spectrum disabled. Fundamental tuned crystals
only
Input capacitance (except crystal pins)
Crystal input capacitance (all internal caps off)
Crystal output capacitance (all internal caps off)
Power up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min
3.0
–40
--
25.1
--
10
10
0.005
Max
3.6
100
15
25.1
7
14
14
500
Unit
V
°C
pF
MHz
pF
pF
pF
ms
DC Electrical Characteristics
(Tj = -40 to 100°C)
Parameter
V
IL
V
IH
V
OL
V
OH
I
ILPDOE
I
IHPDOE
I
ILSR
I
IHSR
I
DD
I
OZ
I
PD
R
UP
R
DN
Rf
Description
Input low voltage
PD#/OE and SSON# pins
Input high voltage
PD#/OE and SSON# pins
Output high voltage, CMOS
levels
Test Conditions
CMOS levels, 30% of V
DD
V
DD
= 3.0V–3.6V
CMOS levels, 70% of V
DD
V
DD
= 3.0V–3.6V
V
DD
= 3.0V–3.6V, I
OH
= –8 mA
Min
--
0.7*
V
DD
0.4
V
DD
– 0.4
--
--
--
--
--
--
--
1
80
80
100
--
10
10
10
50
50
50
50
6
150
150
--
Max
0.3*
V
DD
Unit
V
V
V
V
μA
μA
μA
μA
mA
μA
μA
MΩ
kΩ
kΩ
kΩ
Output low voltage, OUT pin V
DD
= 3.0V–3.6V, I
OL
= 8 mA
Input low current, PD#/OE pin V
IN
= V
SS
(Internal pull up = 3 MΩ typical)
Input high current, PD#/OE
pin
V
IN
= V
DD
(Internal pull up = 100 kΩ typical)
Input low current, SSON# pin V
IN
= V
SS
(Internal pull down = 100 kΩ typical)
Input high current, SSON#
pin
Supply current
V
IN
= V
DD
(Internal pull down = 100 kΩ typical)
No load, V
DD
= 3.0V–3.6V, Fout = 170 MHz
Output leakage current, OUT V
DD
= 3.0V–3.6V, output disabled with OE
pin
Standby current
Pull up resistor on PD#/OE
pin
V
DD
= 3.0V–3.6V, device powered down with PD#
V
DD
= 3.0 to 3.6V, measured at V
IN
=V
SS
V
DD
= 3.0V–3.6V, measured at V
IN
= 0.7V
DD
Pull down resistor on SSON# V
DD
= 3.0V–3.6V, measured at V
IN
= 0.5V
DD
and OUT pins
Crystal feedback resistor
V
DD
= 3.0V–3.6V, measured at X
IN
= 0.
Document #: 38-07363 Rev. *E
Page 5 of 10
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