Frequency select. When HIGH, the output frequency is 7.5 times of the
crystal frequency. When LOW, the output frequency is 6.25 times of the
crystal frequency
Differential clock output
Description
3.3 V or 2.5 V power supply. All supply current flows through pin 1
6,7
CLK#, CLK
LVPECL output
Document #: 001-15705 Rev. *G
Page 3 of 12
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CY2XP24
Frequency Table
Inputs
Crystal Frequency (MHz)
25
25
F_SEL
1
0
PLL Multiplier Value
7.5
6.25
Output Frequency (MHz)
187.5
156.25
Absolute Maximum Conditions
Parameter
V
DD
V
IN[1]
T
S
T
J
ESD
HBM
UL–94
JA[2]
Description
Supply voltage
Input voltage, DC
Temperature, vtorage
Temperature, junction
ESD protection (human body model)
Flammability rating
Thermal resistance, junction to ambient
JEDEC STD 22-A114-B
At 1/8 in.
0 m/s airflow
1 m/s airflow
2.5 m/s airflow
Relative to V
SS
Non operating
Condition
–
Min
–0.5
–0.5
–65
–
2000
V–0
100
91
87
C
/ W
Max
4.4
V
DD
+ 0.5
150
135
–
Unit
V
V
C
C
V
Operating Conditions
Parameter
V
DD
T
A
T
PU
3.3 V supply voltage
2.5 V supply voltage
Ambient temperature, commercial
Ambient temperature, industrial
Power-up time for all V
DD
to reach minimum specified voltage (ensure power ramps
are monotonic)
Description
Min
3.135
2.375
0
-40
0.05
Max
3.465
2.625
70
85
500
Unit
V
V
C
C
ms
DC Electrical Characteristics
Parameter
I
DD
Description
Test Conditions
Min
–
–
–
–
Typ
–
–
–
–
–
–
–
Max
125
120
150
145
V
DD
–0.75
V
DD
–1.625
1000
Unit
V
V
V
V
V
V
mV
Power supply current with output V
DD
= 3.465 V, F
OUT
= 187.5 MHz,
unterminated
output unterminated
V
DD
= 2.625 V, F
OUT
= 187.5 MHz,
output unterminated
I
DDT
Power supply current with output V
DD
= 3.465 V, F
OUT
= 187.5 MHz,
terminated
output terminated
V
DD
= 2.625V, F
OUT
= 187.5 MHz,
output terminated
V
OH
V
OL
V
OD1
LVPECL output high voltage
LVPECL output low voltage
LVPECL Peak-to-peak output
voltage swing
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
to V
DD
–1.15
V
DD
– 2.0 V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
to V
DD
–2.0
V
DD
– 2.0 V
V
DD
= 3.3 V or 2.5 V, R
TERM
= 50
to
V
DD
– 2.0 V
600
Note
1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document #: 001-15705 Rev. *G
Page 4 of 12
[+] Feedback
CY2XP24
DC Electrical Characteristics
(continued)
Parameter
V
OD2
V
OCM
V
IH
V
IL
I
IH
I
IL
C
IN
[3]
Description
LVPECL output voltage swing
(V
OH
- V
OL
)
LVPECL output common mode
voltage (V
OH
+ V
OL
)/2
Input high voltage
Input low voltage
Input high current
Input low current
Input capacitance, F_SEL
Pin capacitance, XIN & XOUT
Test Conditions
V
DD
= 2.5 V, R
TERM
= 50
to
V
DD
– 1.5 V
V
DD
= 2.5 V, R
TERM
= 50
to
V
DD
– 1.5 V
Min
500
1.2
0.7 x V
DD
–0.3
Typ
–
–
–
–
–
–
15
4.5
Max
1000
–
V
DD
+ 0.3
0.3 x V
DD
115
–
–
–
Unit
mV
V
V
V
µA
µA
pF
pF
F_SEL = V
DD
F_SEL = V
SS
–
–50
–
–
C
INX[3]
AC Electrical Characteristics
[4]
Parameter
F
OUT
T
R
, T
F[5]
T
Jitter()[6]
T
DC[7]
T
LOCK
T
LFS
Description
Output frequency
Output rise/fall time
RMS phase jitter (random)
Duty cycle
Startup time
20 % to 80 % of full swing
156.25 MHz, (1.875 – 20 MHz), 3.3 V
156.25 MHz, (12 kHz – 20 MHz), 3.3 V
Measured at zero crossing point
Time for CLK to reach valid frequency
measured from the time
V
DD
= V
DD
(min.)
Time for CLK to reach valid frequency
from F_SEL pin change
Conditions
Min
156.25
–
–
–
45
–
Typ
–
0.5
0.33
0.6
–
–
Max
187.5
1.0
–
–
55
5
Unit
MHz
ns
ps
ps
%
ms
Re-lock time
–
–
1
ms
Recommended Crystal Specifications
[7]
Parameter
Mode
F
ESR
C
0
Mode of oscillation
Frequency
Equivalent series resistance
Shunt capacitance
Description
Min
25
–
–
Max
25
50
7
Unit
MHz
pF
Fundamental
Notes
3. Not 100% tested, guaranteed by design and characterization.
4. Characterized using an 18 pF parallel resonant crystal.
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