Maximum ESD Protection .............................................. 2 kV
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
in
and V
out
should be constrained to the range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
[2]
V
DD
= 3.3 V ± 5% or 2.5 V ± 5%, V
DDC
= 3.3 V ± 5% or 2.5 V ± 5%, T
A
= –40
C
to +85
C
Parameter
V
IL
V
IH
I
IL
I
IH
V
PP
V
CMR
V
OL
V
OH
I
DDQ
I
DD
Description
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
[4]
PECL_CLK
Output Low Voltage
[5, 6, 7]
Output High Voltage
[5, 6, 7]
Quiescent Supply Current
Dynamic Supply Current
V
DD
= 3.3 V, Outputs @ 150 MHz,
CL = 15 pF
V
DD
= 3.3 V, Outputs @ 200 MHz,
CL = 15 pF
V
DD
= 2.5 V, Outputs @ 150 MHz,
CL = 15 pF
V
DD
= 2.5 V, Outputs @ 200 MHz,
CL = 15 pF
Z
out
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
I
OL
= 20 mA
I
OH
= –20 mA, V
DDC
= 3.3 V
I
OH
= –20 mA, V
DDC
= 2.5 V
Conditions
Min
V
SS
2.0
–
–
500
V
DD
– 1.4
V
DD
– 1.0
–
2.4
1.8
–
–
–
–
–
8
10
–
Typ
–
–
–
–
–
–
–
–
–
–
5
285
335
200
240
12
15
4
Max
0.8
V
DD
–200
200
1000
V
DD
– 0.6
V
DD
– 0.6
0.5
–
–
7
–
–
–
–
16
20
–
pF
Unit
V
V
µA
µA
mV
V
V
V
V
V
mA
mA
Notes
2.
Multiple Supplies:
The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification. Driving series or parallel terminated 50
(or 50
to V
DD
/2) transmission lines
5. Outputs driving 50
transmission
lines.
6. See
Figure 1 on page 5
and
Figure 2 on page 5.
7. 50% input duty cycle.
Document #: 38-07283 Rev. *E
Page 3 of 10
[+] Feedback
CY29940
AC Parameters
[8]
V
DD
= 3.3 V ± 5% or 2.5 V ± 5%, V
DDC
= 3.3 V ± 5% or 2.5 V ± 5%, T
A
= –40
C
to +85
C
Parameter
F
max
t
PD
Description
Input Frequency
PECL_CLK to Q Delay
[9, 10, 11]
150 MHz V
DD
= 3.3 V, 85
C
V
DD
= 3.3 V, 70
C
V
DD
= 2.5 V, 85
C
V
DD
= 2.5 V, 70
C
t
PD
LVCMOS to Q Delay
[9, 10, 11]
150 MHz
V
DD
= 3.3 V, 85
C
V
DD
= 3.3 V, 70
C
V
DD
= 2.5 V, 85
C
V
DD
= 2.5 V, 70
C
t
J
FoutDC
T
skew
T
skew
(pp)
T
skew
(pp)
T
skew
(pp)
t
R
/t
F
Total Jitter
Output Duty
Cycle
[9, 10, 12]
Skew
[9, 10]
V
DD
= 3.3 V @ 150 MHz
FCLK < 134 MHz
FCLK > 134 MHz
Output-to-Output
V
DD
= 3.3 V
V
DD
= 2.5 V
Part-to-Part Skew
[13]
Part-to-Part Skew
[13]
Part to Part
Skew
[14]
PECL, V
DDC
= 3.3 V
PECL, V
DDC
= 2.5 V
TCLK, V
DDC
= 3.3 V
TCLK, V
DDC
= 2.5 V
PECL_CLK
TCLK
Output Clocks Rise/Fall Time
[9, 10]
0.7 V to 2.0 V, V
DDC
= 3.3 V
0.5 V to 1.8 V, V
DDC
= 2.5 V
Conditions
–
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
Min
–
2.0
2.1
1.9
2.0
2.5
2.6
2.5
2.6
1.9
2.0
1.8
1.8
2.5
2.5
2.3
2.3
–
–
–
–
–
–
–
–
–
–
–
0.3
0.3
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
60
–
–
–
–
–
–
–
–
–
Max
200
3.2
3.4
3.1
3.2
5.2
5
5
5
3
3.2
2.9
3.1
4
4
3.8
3.8
10
55
60
150
200
1.4
2.2
1.2
1.7
850
750
1.1
1.2
ns
ps
ns
ns
ps
ps
%
ns
Unit
MHz
ns
Notes
8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
9. Outputs driving 50
transmission
lines.
10. See
Figure 1 on page 5
and
Figure 2 on page 5.
11. Parameters tested @ 150 MHz.
12. 50% input duty cycle.
13. Across temperature and voltage ranges, includes output skew.
14. For a specific temperature and voltage, includes output skew.
Document #: 38-07283 Rev. *E
Page 4 of 10
[+] Feedback
CY29940
Figure 1. LVCMOS_CLK CY29940 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
CY29940 DUT
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29940 Test Reference for V
CC
= 3.3 V and V
CC
= 2.5 V
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
CY29940 DUT
Zo = 50 ohm
Zo = 50 ohm
R
T
= 50 ohm
R
T
= 50 ohm
VTT
VTT
Figure 3. Propagation Delay (TPD) Test Reference
PECL_CLK
PECL_CLK
V
PP
V
CMR
VCC
Q
VCC /2
t
PD
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
Yamaha Motor Group旗下的i-PULSE有限公司日前已与华尔莱科技（Valor）结为合作伙伴关系，基于Valor的vPlan生产规划工具向i-PULSE组装设备的使用者提供完整的从设计到制造的NPI解决方案。在近期日本东京举办的Protec展会（6/11-6/13）上，i-PULSE首度展出了该新产品并将直接向其客户进行销售。 新产品的名称为“iPlan”，它将提供一系...[详细]
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