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CY29351

2.5V or 3.3V, 200 MHz,

9-Output Zero Delay Buffer

Features

■

Functional Description

The CY29351 is a low voltage high performance 200 MHz

PLL-based zero delay buffer designed for high speed clock distri-

bution applications.

The CY29351 features LVPECL and LVCMOS reference clock

inputs and provides nine outputs partitioned in four banks of one,

one, two, and five outputs. Bank A divides the VCO output by two

or four while the other banks divide by four or eight per SEL(A:D)

settings (Table

3, “Function Table,”

on page 3). These dividers

enable output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each

LVCMOS compatible output can drive 50Ω series or parallel

terminated transmission lines. For series terminated trans-

mission lines, each output can drive one or two traces giving the

device an effective fanout of 1:18.

The PLL is ensured stable given that the VCO is configured to

run between 200 MHz to 500 MHz. This allows a wide range of

output frequencies from 25 MHz to 200 MHz. For normal

operation, the external feedback input, FB_IN, is connected to

one of the outputs. The internal VCO is running at multiples of

the input reference clock set by the feedback divider (Table

2,

“Frequency Table,”

on page 3).

When PLL_EN# is LOW, PLL is bypassed and the reference

clock directly feeds the output dividers. This mode is fully static

and the minimum input clock frequency specification does not

apply.

Output Frequency Range: 25 MHz to 200 MHz

Input Frequency Range: 25 MHz to 200 MHz

2.5V or 3.3V Operation

Split 2.5V and 3.3V Outputs

±2.5% Max Output Duty Cycle Variation

Nine Clock Outputs: Drive up to 18 Clock Lines

Two Reference Clock Inputs: LVPECL or LVCMOS

150-ps Max Output-Output Skew

Phase-locked Loop (PLL) Bypass Mode

Spread Aware

Output Enable or Disable

Pin-compatible with MPC9351

Industrial Temperature Range: –40°C to +85°C

32-pin 1.0-mm TQFP Package

Logic Block Diagram

SELA

PLL_EN

REF_SEL

TCLK

PECL_CLK

Phase

Detector

VCO

200 -

500 MHz

÷2 / ÷4

QA

LPF

÷4 / ÷8

QB

FB_IN

SELB

SELC

OE#

÷4 / ÷8

QC0

QC1

÷4 / ÷8

SELD

QD0

QD1

QD2

QD3

QD4

Cypress Semiconductor Corporation

Document Number: 38-07475 Rev. *C

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Revised March 17, 2009

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CY29351

Pinout

Figure 1. Pin Diagram - 32-Pin TQFP Package

REF_SEL

PLL_EN

VDDQB

27

TCLK

VSS

25

QA

28

QB

26

32

31

30

29

A VD D

F B _IN

SE LA

SE LB

SELC

SELD

AVSS

PEC L_C LK

1

2

3

4

5

6

7

8

C Y29351

24

23

22

21

20

19

18

17

QC0

VD D Q C

QC1

VSS

QD0

VD D Q D

QD1

VSS

9

10

11

12

13

14

QD3

15

VDDQD

VDD

QD4

VSS

OE#

Table 1. Pin Definitions - 32-Pin TQFP Package

[1]

Name

I/O

Type

8

9

30

28

26

22, 24

2

10

31

32

3, 4, 5, 6

27

23

15, 19

1

11

7

PECL_CLK

TCLK

QA

QB

QC(1,0)

FB_IN

OE#

PLL_EN

REF_SEL

SEL(A:D)

VDDQB

VDDQC

VDDQD

AVDD

VDD

AVSS

I, PU

I, PD

O

I, PD

I, PU

I, PD

Supply

PECL_CLK# I, PU/PD

PECL_CLK#

QD2

16

Description

LVPECL LVPECL reference clock input

LVPECL LVPECL reference clock input. Weak pull up to VDD/2.

LVCMOS LVCMOS/LVTTL reference clock input

LVCMOS Clock output bank A

LVCMOS Clock output bank B

LVCMOS Clock output bank C

LVCMOS Clock output bank D

LVCMOS Feedback clock input. Connect to an output for normal operation. This

input should be at the same voltage rail as input reference clock

LVCMOS Output enable/disable input

LVCMOS PLL enable/disable input

LVCMOS Reference select input

LVCMOS Frequency select input, bank (A:D)

VDD

Ground

2.5V or 3.3V power supply for bank B output clock

[2,3]

2.5V or 3.3V power supply for bank C output clocks

[2,3]

2.5V or 3.3V power supply for bank D output clocks

[2,3]

2.5V or 3.3V power supply for PLL

[4,5]

2.5V or 3.3V power supply for core, inputs, and bank A output clock

[2,3]

Analog ground

Common ground

12, 14, 16, 18, 20 QD(4:0)

13, 17, 21, 25, 29 VSS

Notes

1. PU = Internal pull up, PD = Internal pull down.

2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the

high-frequency filtering characteristics are cancelled by the lead inductance of the traces.

3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.

4. Driving one 50Ω parallel terminated transmission line to a termination voltage of V

TT

. Alternatively, each output drives up to two 50

Ω

series terminated

transmission lines.

5. Inputs have pull up or pull down resistors that affect the input current.

Document Number: 38-07475 Rev. *C

Page 2 of 10

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CY29351

Table 2. Frequency Table

Feedback Output Divider

÷2

÷4

÷8

Table 3. Function Table

Control

REF_SEL

PLL_EN

OE#

SELA

SELB

SELC

SELD

Default

0

1

0

PCLK

Bypass mode, PLL disabled. The input clock

connects to the output dividers

Outputs enabled

÷

2 (bank A)

÷

4 (bank B)

÷

4 (bank C)

÷

4 (bank D)

0

TCLK

PLL enabled. The VCO output connects to the output

dividers

Outputs disabled (three-state), VCO running at its

minimum frequency

÷

4 (bank A)

÷

8 (bank B)

÷

8 (bank C)

÷

8 (bank D)

1

VCO

Input Clock * 2

Input Clock * 4

Input Clock * 8

Input Frequency Range

(AVDD = 3.3V)

100 MHz to 200 MHz

50 MHz to 125 MHz

25 MHz to 62.5 MHz

Input Frequency Range

(AVDD = 2.5V)

100 MHz to 190 MHz

50 MHz to 95 MHz

25 MHz to 47.5 MHz

Absolute Maximum Conditions

Parameter

V

DD

V

DD

V

IN

V

OUT

V

TT

LU

R

PS

T

S

T

A

T

J

Ø

JC

Ø

JA

ESD

H

FIT

Description

DC supply voltage

DC operating voltage

DC input voltage

DC output voltage

Output termination voltage

Latch-up immunity

Power supply ripple

Temperature, storage

Temperature, operating ambient

Temperature, junction

Dissipation, junction to case

Dissipation, junction to ambient

ESD protection (human body model)

Failure in time

Manufacturing test

Functional

Ripple frequency < 100 kHz

Non Functional

Functional

2000

10

Functional

Relative to V

SS

Relative to V

SS

Condition

Min

–0.3

2.375

–0.3

–

200

–

–65

–40

–

42

105

–

Max

5.5

3.465

V

DD

+ 0.3

V

DD

+ 0.3

V

DD

÷

2

–

150

+150

+85

+150

Unit

V

mA

mVp-p

°C

°C/W

Volts

ppm

Document Number: 38-07475 Rev. *C

Page 3 of 10

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CY29351

DC Electrical Specifications

(V

DD

= 2.5V ± 5%, T

A

= –40°C to +85°C)

Parameter

V

IL

V

IH

V

PP

V

CMR

V

OL

V

OH

I

IL

I

IH

I

DDA

I

DDQ

I

DD

C

IN

Z

OUT

Description

Input voltage, low

Input voltage, high

Peak-Peak input voltage

Common mode range

[6]

Output voltage, low

[4]

Output voltage, high

[4]

Input current,

low

[5]

high

[5]

LVCMOS

LVPECL

I

OL

= 15mA

I

OH

= –15mA

V

IL

= V

SS

V

IL

= V

DD

AVDD only

All V

DD

pins except AVDD

Outputs loaded at 100 MHz

Outputs loaded at 200 MHz

Input pin capacitance

Output impedance

Condition

Min

–

1.7

250

1.0

–

1.8

–

14

Typ

–

5

–

180

210

4

18

Max

0.7

V

DD

+0.3

1000

V

DD

– 0.6

0.6

–

–100

100

10

7

–

22

pF

Ω

Unit

V

mV

V

μA

mA

PLL supply current

Quiescent supply current

Dynamic supply current

DC Electrical Specifications

(V

DD

= 3.3V ± 5%, T

A

= –40°C to +85°C)

Parameter

V

IL

V

IH

V

PP

V

CMR

V

OL

V

OH

I

IL

I

IH

I

DDA

I

DDQ

I

DD

C

IN

Z

OUT

Description

Input voltage, low

Input voltage, high

Peak-Peak input voltage

Common mode range

[6]

Output Voltage, Low

[4]

Output voltage, high

Input current,

low

[5]

[4]

Condition

LVCMOS

LVPECL

I

OL

= 24 mA

I

OL

= 12 mA

I

OH

= –24 mA

V

IL

= V

SS

V

IL

= V

DD

AVDD only

All VDD pins except AVDD

Outputs loaded at 100 MHz

Outputs loaded at 200 MHz

Min

–

2.0

250

1.0

–

2.4

–

12

Typ

–

5

–

270

300

4

15

Max

0.8

V

DD

+ 0.3

1000

V

DD

– 0.6

0.55

0.30

–

–100

100

10

7

–

18

Unit

V

mV

V

μA

mA

pF

Ω

Input current, high

[5]

PLL supply current

Quiescent supply current

Dynamic supply current

Input pin capacitance

Output impedance

Note

6. V

CMR

(DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the V

CMR

range and the input swing

is within the V

PP

(DC) specification.

Document Number: 38-07475 Rev. *C

Page 4 of 10

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CY29351

AC Electrical Specifications

(V

DD

= 2.5V ± 5%, T

A

= –40°C to +85°C)

[7]

Parameter

f

VCO

f

in

Description

VCO frequency

Input frequency

÷2

feedback

÷4

feedback

÷8

feedback

Bypass mode (PLL_EN = 0)

f

refDC

V

PP

V

CMR

t

r

, t

f

MAX

Input duty cycle

Peak-Peak input voltage

Common mode

range

[8]

TCLK input rise/fall time

Maximum output frequency

LVPECL

0.7V to 1.7V

÷2

output

÷4

output

÷8

output

DC

t

r

, t

f

t

(φ)

t

sk(O)

t

PLZ, HZ

t

PZL, ZH

BW

Output duty cycle

Output rise/fall times

f

MAX

< 100 MHz

f

MAX

> 100 MHz

0.6V to 1.8V

PCLK to FB_IN

Output-to-Output skew

Output disable time

Output enable time

PLL closed loop bandwidth (–3dB)

÷2

feedback

÷4

feedback

÷8

feedback

t

JIT(CC)

t

JIT(PER)

t

JIT(φ)

t

LOCK

Cycle-to-Cycle jitter

Period jitter

I/O phase jitter

Maximum PLL lock time

Same frequency

Multiple frequencies

Same frequency

Multiple frequencies

Propagation delay (static phase offset) TCLK to FB_IN

Condition

Min

200

100

50

25

0

25

500

1.2

–

100

50

25

47.5

45

0.1

–100

–

Typ

–

2.2

0.85

0.6

–

175

–

Max

380

190

95

47.5

200

75

1000

V

DD

– 0.6

1.0

190

95

47.5

52.5

55

1.0

100

150

10

–

150

250

100

175

–

1

ps

ms

ps

ns

MHz

ns

ps

%

mV

V

ns

MHz

Unit

MHz

Notes

7. AC characteristics apply for parallel output termination of 50Ω to V

TT

. Parameters are guaranteed by characterization and are not 100% tested.

8. V

CMR

(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V

CMR

range and the input swing lies

within the V

PP

(AC) specification. Violation of V

CMR

or V

PP

impacts static phase offset t(φ).

Document Number: 38-07475 Rev. *C

Page 5 of 10

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