CY25811/12/14
Spread Spectrum Clock Generator
Features
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Applications
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4 to 32 MHz input frequency range
4 to 128 MHz output frequency range
Accepts clock, crystal, and resonator inputs
1x, 2x, and 4x frequency multiplication:
❐
CY25811: 1x; CY25812: 2x; CY25814: 4x
Center and down spread modulation
Low power dissipation:
❐
3.3V = 52 mW - typ at 6 MHz
❐
3.3V = 60 mW - typ at12 MHz
❐
3.3V = 72 mW - typ at 24 MHz
Low cycle to cycle jitter:
❐
8 MHz = 480 ps-max
❐
16 MHz = 400 ps-max
❐
32 MHz = 450 ps-max
Available in 8-pin SOIC and TSSOP packages
Commercial and industrial temperature ranges
Printers and MFPs
LCD panels
Digital copiers
PDAs
CD-ROM, VCD, and DVD
Networking, LAN, and WAN
Scanners
Modems
Embedded digital systems
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Benefits
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Peak EMI reduction by 8 to 16 dB
Fast time to market
Cost reduction
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Logic Block Diagram
300K
XIN
1
8pF
REFERENCE
DIVIDER
PD and
CP
LF
XOUT
8
8pF
MODULATION
CONTROL
VDD
7
VCO
COUNTE
R
VCO
VSS
2
6
INPUT
DECODER
LOGIC
3
4
COUNTER
and
MUX
5
SSCLK
FRSEL
S1
S0
Cypress Semiconductor Corporation
Document Number: 38-07112 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 22, 2008
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CY25811/12/14
Pinouts
Figure 1. Pin Diagram - 8 Pin SOIC/TSSOP
XIN/CLKIN
1
VSS
2
S1
3
S0
4
CY25811
CY25812
CY25814
8
XOUT
VDD
FRSEL
SSCLK
7
6
5
Table 1. Pin Definition - 8 Pin SOIC/TSSOP
Pin No.
Name
Type
1
2
3
4
5
6
7
8
Xin/CLK
VSS
S1
S0
SSCLK
FRSEL
VDD
XOUT
Power supply ground.
Description
Crystal, ceramic resonator or clock input pin
Digital Spread% control pin.
3-Level input (H-M-L). Default = M.
Digital Spread% control pin.
3-Level input (H-M-L). Default = M.
Spread Spectrum output clock.
Input frequency range selection digital control input.
3-Level input (H-M-L). Default = M.
Positive power supply.
Crystal or ceramic resonator output pin.
The user selects Center Spread or Down Spread frequency
modulation based on four discrete values of Spread % for each
Spread mode with the option of a Non Spread mode for system
test and verification purposes.
The CY25811/12/14 products are available in an 8 pin SOIC -150
mil package with a commercial operating temperature range of
0 to 70°C and Industrial Temperature range of –40 to 85°C. Refer
to
CY25568
for multiple clock output options such as modulated
and unmodulated clock outputs or Power-down function. For
Automotive applications, refer to
CY25811/12/14SE data sheets.
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock
Generator (SSCG) ICs used for the purpose of reducing electro-
magnetic interference (EMI) found in today’s high speed digital
electronic systems.
The devices use a Cypress proprietary phase-locked loop (PLL)
and Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the input clock. By frequency
modulating the clock, the measured EMI at the fundamental and
harmonic frequencies is greatly reduced.
This reduction in radiated energy significantly reduces the cost
of complying with regulatory agency requirements and improves
time to market without degrading system performance.
The input frequency range is 4 to 32 MHz and accepts clock,
crystal and ceramic resonator inputs. The output clock can be
selected to produce 1x, 2x, or 4x multiplication of the input
frequency with Spread Spectrum Frequency Modulation.
The use of 2x or 4x frequency multiplication eliminates the need
for higher order crystals and enables the user to generate up to
128 MHz Spread Spectrum Clock (SSC) by using only first order
crystals. This reduces the cost while improving the system clock
accuracy, performance, and complexity.
Input Frequency Range and Selection
The CY25811/12/14 input frequency range is 4 to 32 MHz. This
range is divided into three segments and controlled by a 3-Level
FRSEL pin as given in
Table 2.
Table 2. Input Frequency Selection
FRSEL
0
1
M
Input Frequency Range
4.0 to 8.0 MHz
8.0 to 16.0 MHz
16.0 to 32.0 MHz
Document Number: 38-07112 Rev. *G
Page 2 of 13
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CY25811/12/14
Spread Percentage Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread, and No-Spread functions. The amount of Spread
percentage is selected using 3-Level. S0 and S1 digital inputs and Spread percent values are given in
Table 3.
Table 3. Spread Percent Selection
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
Center
(%)
4-5
5-6
6-7
7-8
8-10
10-12
12-14
14-16
16-20
20-24
24-28
28-32
0
0
0
0
1
1
1
1
M
M
M
M
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
±1.4
±1.3
±1.2
±1.1
S1 = 0
S0 = M
Center
(%)
± 1.2
± 1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
±1.2
±1.1
± 0.9
± 0.9
S1 = 0
S0 = 1
Center
(%)
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
± 0.6
± 0.5
± 0.5
± 0.4
S1 = M
S0 = 0
Center
(%)
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
± 0.5
± 0.4
± 0.4
± 0.3
S1 = 1
S0 = 1
Down
(%)
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
–3.0
–2.7
–2.5
–2.3
S1 = 1
S0 = 0
Down
(%)
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
–2.2
–1.9
–1.8
–1.7
S1 = M
S0 = 1
Down
(%)
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
–1.9
–1.7
–1.5
–1.4
S1 = 1
S0 = M
Down
(%)
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
–0.7
–0.6
–0.6
–0.5
S1 = M
S0 = M
No Spread
0
0
0
0
0
0
0
0
0
0
0
0
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0”, and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic detects
nine different logic states.
S0, S1, and FRSEL pins include an on chip 20K (10K and 10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown here:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
DD
.
Figure 2
illustrates how to implement 3–Level Logic.
Figure 2. 3–Level Logic
LOGIC
LOW (0)
S0, S1
and
FRSEL
to VSS
Modulation Rate
SSCGs use frequency modulation (FM) to distribute energy over
a specific band of frequencies. The maximum frequency of the
clock (fmax), and minimum frequency of the clock (fmin)
determine this band of frequencies. The time required to
transition from fmin to fmax and back to fmin is the period of the
Modulation Rate. The Modulation Rate of SSCG clocks are
generally referred to in terms of frequency, or:
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine
the Modulation Rate.
In CY25811/2/4 devices, the (Spread Spectrum) modulation
Rate, fmod, is given by the following formula:
fmod = fin/DR
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
LOGIC
MIDDLE (M)
S0, S1
and
FRSEL
UNCONNECTED
Here fmod is the Modulation Rate, fin is the Input Frequency, and
DR is the Divider Ratio as given in
Table 4.
Note that Input
Frequency Range is set by FRSEL.
Table 4. Modulation Rate Divider Ratios
FRSEL
0
Input Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
Divider Ratio
(DR)
128
256
512
VSS
1
M
Document Number: 38-07112 Rev. *G
Page 3 of 13
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CY25811/12/14
Input and Output Frequency Selection
The relationship between input frequency and output frequency in device selection and FRSEL setting is given in
Table 5.
As shown,
the input frequency range is selected by FRSEL and is the same for CY25811, CY25812, and CY25814. The selection of CY25811
(1x), CY25812 (2x), or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to input
frequency (XIN, Pin-1).
Table 5. Input and Output Frequency Selection
Input Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
4 to 8
8 to 16
16 to 32
4 to 8
8 to 16
16 to 32
FRSEL
0
1
M
0
1
M
0
1
M
Product
CY25811
CY25811
CY25811
CY25812
CY25812
CY25812
CY25814
CY25814
CY25814
Multiplication
1x
1x
1x
2x
2x
2x
4x
4x
4x
Output Frequency Range
(MHz)
4 to 8
8 to 16
16 to 32
8 to 16
16 to 32
32 to 64
16 to 32
32 to 64
64 to 128
Document Number: 38-07112 Rev. *G
Page 4 of 13
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CY25811/12/14
Absolute Maximum Conditions
(both Commercial and Industrial Grades)
[1,2]
Parameter
V
DD
V
IN
T
S
T
A1
T
A2
T
J
ESD
HBM
UL-94
MSL
Description
Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Operating Ambient
Temperature, Junction
Flammability Rating
Moisture Sensitivity Level
Relative to V
SS
Non Functional
Functional, C-Grade
Functional, I-Grade
Functional
@1/8 in.
Condition
Min
–0.5
–0.5
–65
0
–40
–
2000
V–0
1
Max
4.6
V
DD
+ 0.5
150
70
85
150
–
Unit
V
VDC
°C
°C
°C
°C
V
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
DC Electrical Specifications
(Commercial Grade)
Parameter
V
DD
V
IL
V
IM
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IN2
C
L
I
DD1
I
DD2
I
DD3
Description
3.3 Operating Voltage
Input Low Voltage
Input Middle Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Pin Capacitance
Input Pin Capacitance
Output Load Capacitor
Dynamic Supply Current
Dynamic Supply Current
Dynamic Supply Current
3.3 ± 10%
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
I
OL
= 4 ma, SSCLK Output
I
OL
= 10 ma, SSCLK Output
I
OH
= 4 ma, SSCLK Output
I
OH
= 6 ma, SSCLK Output
XIN (Pin 1) and XOUT (Pin 8)
All Digital Inputs
SSCLK Output
Fin = 12 MHz, no load
Fin = 24 MHz, no load
Fin = 32 MHz, no load
Condition
Min
3.97
0
0.85V
DD
–
–
2.4
2.0
3.5
2.8
–
–
–
–
Max
3.63
0.15V
DD
V
DD
0.4
1.2
–
–
9.0
6.0
15
28
33
40
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
0.40V
DD
0.60V
DD
Notes
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
Document Number: 38-07112 Rev. *G
Page 5 of 13
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