CY25402/CY25422/CY25482
Two PLL Programmable Clock Generator
with Spread Spectrum
Features
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Ability to synthesize nonstandard frequencies with Fractional-N
capability
Three clock outputs with programmable drive strength
Glitch-free outputs while frequency switching
8-pin small outline integrated circuit (SOIC) package
Commercial and Industrial temperature ranges
Two fully integrated phase locked loops (PLLs)
Input frequency range
❐
External crystal: 8 to 48 MHz
❐
External reference: 8 to 166 MHz clock
Reference clock input voltage range
❐
2.5 V, 3.0 V, and 3.3 V for CY25482
❐
1.8 V for CY25402 and CY25422
Wide operating output frequency range
❐
3 to 166 MHz
Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
V
DD
supply voltage options:
❐
2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐
1.8 V for CY25422
Selectable output clock voltages independent of V
DD
:
❐
2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐
1.8 V for CY25422
Frequency select feature with option to select four different
frequencies
Power-down, Output Enable, and SS ON/OFF controls
Low jitter, high accuracy outputs
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Benefits
■
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Multiple high performance PLLs allow synthesis of unrelated
frequencies
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
Application specific programmable EMI reduction using spread
spectrum for clocks
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Suitability for PC, consumer, portable, and networking
applications
Capable of zero parts per million (PPM) frequency synthesis
error
Uninterrupted system operation during clock frequency switch
Application compatibility in standard and low power systems
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Block Diagram
XIN/
EXCLKIN
XOUT
OSC
MUX
and
FS0
FS1
Control
Logic
PLL 2
(SS)
PLL 1
(SS)
Crossbar
Switch
Output
Dividers
and
Drive
Strength
Control
CLK1
REFOUT
CLK2
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12565 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 20, 2011
CY25402/CY25422/CY25482
Contents
Pin Description ................................................................. 3
General Description ......................................................... 5
2 Configurable PLLs .................................................... 5
Input Reference Clocks ............................................... 5
VDD Power Supply Options ........................................ 5
Output Source Selection ............................................. 5
Spread Spectrum Control ............................................ 5
Frequency Select ........................................................ 5
Glitch-Free Frequency Switch ..................................... 5
PD#/OE Mode ............................................................. 5
Output Drive Strength .................................................. 5
Generic Configuration and Custom Frequency ........... 5
Absolute Maximum Conditions ....................................... 6
Recommended Operating Conditions ............................ 6
DC Electrical Specifications ............................................ 7
AC Electrical Specifications ............................................ 8
Recommended Crystal Specification for SMD Package 8
Test and Measurement Setup .......................................... 9
Voltage and Timing Definitions ....................................... 9
Recommended Crystal Specification for
Thru-Hole Package ........................................................... 9
Possible Configurations ............................................. 10
Ordering Code Definitions ......................................... 11
Package Drawing and Dimensions ............................... 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC
®
Solutions ....................................................... 14
Document #: 001-12565 Rev. *F
Page 2 of 14
CY25402/CY25422/CY25482
Table 1. Device Selector Guide
Device
CY25402
CY25482
CY25422
Crystal Input
Yes
No
Yes
EXCKLKIN Input
1.8 V LVCMOS
2.5 V, 3.0 V, 3.3 V LVCMOS
1.8 V LVCMOS
V
DD
2.5 V, 3.0 V, 3.3 V
2.5 V, 3.0 V, 3.3 V
1.8 V
Pin Description
Figure 1. Pin Diagram - CY25402 8-LD SOIC
XIN/
EXCLKIN
V
DD
CLK1
REFOUT/
FS0
1
2
3
4
CY25402
8
7
6
5
XOUT
GND
CLK2/SSON
PD#/OE/FS1
Table 2. Pin Definition - CY25402 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
1
2
3
4
5
6
7
8
V
DD
CLK1
PD#/OE/FS1
CLK2/SSON
GND
XOUT
Name
XIN/EXCLKIN Input
Power
Output
Input
Output/input
Power
Output
IO
Description
Crystal input or 1.8 V External clock input
Power supply: 2.5 V, 3.0 V, or 3.3 V
Programmable clock output with spread spectrum
Multifunction programmable pin: Reference clock output or frequency select pin
Multifunction programmable pin: Power-down, output enable or Frequency select
pin
Multifunction programmable pin: Programmable clock output with spread spectrum
or Spread spectrum ON/OFF control pin
Power supply ground
Crystal output
REFOUT/FS0 Output/input
Document #: 001-12565 Rev. *F
Page 3 of 14
CY25402/CY25422/CY25482
Figure 2. Pin Diagram - CY25482 8-LD SOIC
EXCLKIN
V
DD
CLK1
REFOUT/
FS0
1
2
3
4
CY25482
8
7
6
5
DNU
GND
CLK2/SSON
PD#/OE/FS1
Table 3. Pin Definition - CY25482 (2.5 V, 3.0 V, or 3.3 V Supply)
Pin Number
1
2
3
4
5
6
7
8
V
DD
CLK1
PD#/OE/FS1
CLK2/SSON
GND
DNU
Name
EXCLKIN
Input
Power
Output
Input
Output/input
Power
Output
IO
Description
2.5 V, 3.0 V, or 3.3 V external clock input
Power Supply: 2.5 V, 3.0 V, or 3.3 V
Programmable clock output with spread spectrum
Multifunction programmable pin: Reference clock output or frequency select pin
Multifunction programmable pin: Power-down, output enable or frequency select
pin
Multifunction Programmable pin: Programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
Power supply ground
Do not use this pin
Figure 3. Pin Diagram - CY25422 8-LD SOIC
XIN/
EXCLKIN
V
DD
CLK1
REFOUT/
FS0
REFOUT/FS0 Output/input
1
2
3
4
CY25422
8
7
6
5
XOUT
GND
CLK2/SSON
PD#/OE/FS1
Table 4. Pin Definition - CY25422 (1.8 V Supply)
Pin Number
1
2
3
4
5
6
7
8
V
DD
CLK1
REFOUT/FS0
PD#/OE/FS1
CLK2/SSON
GND
XOUT
Name
XIN/EXCLKIN
Input
Power
Output
Output/input
Input
Output/input
Power
Output
IO
Power supply: 1.8 V
Programmable clock output with spread spectrum
Multifunction programmable pin: reference clock output or frequency select pin
Multifunction programmable pin: power-down, output enable or frequency select
pin
Multifunction programmable pin: programmable clock output with spread spectrum
or spread spectrum ON/OFF control pin
Power supply ground
Crystal output
Description
Crystal input or 1.8 V external clock input
Document #: 001-12565 Rev. *F
Page 4 of 14
CY25402/CY25422/CY25482
General Description
2 Configurable PLLs
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. This gives user an option for this device to be compatible
for different input clock voltage levels in the system.
V
DD
Power Supply Options
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
Table 4
on page 4 shows the
typical rise and fall times for different drive strength settings.
Table 5. Output Drive Strength
Output Drive Strength
Low
Mid Low
Mid High
High
Rise/Fall Time (ns)
(Typical Value)
6.8
3.4
2.0
1.0
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
Spread Spectrum Control
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Document #: 001-12565 Rev. *F
Page 5 of 14
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