CY2314ANZ
14 Output, 3.3V SDRAM Buffer for
Desktop PCs with 3 DIMMs
Features
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Functional Description
The CY2314ANZ is a 3.3V buffer designed to distribute high
speed clocks in desktop PC applications. The part has 14
outputs, 12 of which can be used to drive up to three SDRAM
DIMMs. The remaining can be used for external feedback to a
PLL. The device operates at 3.3V and outputs can run up to 100
MHz.
The CY2314ANZ also includes a serial interface which can
enable or disable each output clock. On power up, all output
clocks are enabled. A separate Output Enable pin facilitates
testing on ATE.
One input to 14 output buffer or driver
Supports up to three SDRAM DIMMs
Two additional outputs for feedback
Serial interface for output control
Low skew outputs
Up to 100 MHz operation
Multiple V
DD
and V
SS
pins for noise reduction
Dedicated OE pin for testing
Low EMI outputs
28-pin SOIC (300-mil) package
3.3V operation
Logic Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDRAM3
Serial Interface
Decoding
SCLOCK
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDATA
OE
Cypress Semiconductor Corporation
Document #: 38-07143 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 10, 2008
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CY2314ANZ
Pin Configuration
Figure 1. 28-Pin SOIC Top View
V
DD
SDRAM0
SDRAM1
V
SS
V
DD
SDRAM2
SDRAM3
V
SS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
V
DDIIC
SDATA
V
DD
SDRAM11
SDRAM10
V
SS
V
DD
SDRAM9
SDRAM8
V
SS
OE
SDRAM7
SDRAM6
SDRAM13
V
SSIIC
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Device Functionality
OE
0
1
SDRAM [0-13]
High-Z
1 x BUF_IN
Serial Configuration Map
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The serial bits are read by the clock driver in the following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Table 2. Byte 1: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
27
26
23
22
--
--
19
18
Description
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
Reserved, Drive to 0
Reserved, Drive to 0
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
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Reserved and unused bits should be programmed to “0”
Serial interface address for the CY2314ANZ is:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Table 1. Byte 0: SDRAM Active/Inactive Register
(1
= Enable, 0 = Disable), Default = Enabled
Bit
Pin #
Description
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
Reserved, Drive to 0
Reserved, Drive to 0
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
Bit 7 11
Bit 6 10
Bit 5 --
Bit 4 --
Bit 3 7
Bit 2 6
Bit 1 3
Bit 0 2
Table 3. Byte 2: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
17
12
--
--
--
--
--
--
Description
SDRAM13 (Active/Inactive)
SDRAM12 (Active/Inactive)
Reserved, Drive to 0
Reserved, Drive to 0
Reserved, Drive to 0
Reserved, Drive to 0
Reserved, Drive to 0
Reserved, Drive to 0
Document #: 38-07143 Rev. *B
Page 2 of 8
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CY2314ANZ
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except BUF_IN) ....... –0.5V to V
DD
+ 0.5V
DC Input Voltage (BUF_IN) ............................–0.5V to +7.0V
Storage Temperature ................................. –65
°
C to +150
°
C
Junction Temperature................................................. 150
°
C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions
[1]
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Power up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
Description
Min
3.135
0
Max
3.465
70
30
7
50
Unit
V
°
C
pF
pF
ms
Electrical Characteristics
Over the Operating Range
Parameter
V
IL
V
ILiic
V
IH
I
IL
I
IL
I
IH
V
OL
V
OH
I
DD
I
DD
I
DD
I
DD
I
DDS
Description
Input LOW Voltage
[2]
Input LOW Voltage
Input HIGH
Voltage
[2]
V
IN
= 0V
V
IN
= 0V
V
IN
= V
DD
I
OL
= 25 mA
I
OH
= –36 mA
Unloaded outputs, 100 MHz
Loaded outputs, 100 MHz
Unloaded outputs, 66.67 MHz
Loaded outputs, 66.67 MHz
BUF_IN=V
DD
or V
SS
All other inputs at V
DD
2.4
200
290
150
185
500
–10
Input LOW Current
(BUF_IN input)
Input LOW Current
(Except BUF_IN Pin)
Input HIGH Current
Output LOW Voltage
[3]
Output HIGH Voltage
[3]
Supply Current
[3]
Supply Current
[3]
Supply Current
[3]
Supply Current
[3]
Supply Current
Test Conditions
Except serial interface pins
For serial interface pins only
2.0
–10
10
100
10
0.4
Min
Max
0.8
0.7
Unit
V
V
V
μA
μA
μA
V
V
mA
mA
mA
mA
μA
Notes
1. Electrical parameters are guaranteed under the operating conditions specified.
2. BUF_IN input has a threshold voltage of V
DD
/2.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07143 Rev. *B
Page 3 of 8
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CY2314ANZ
Switching Characteristics
[4]
Over the Operating Range
Parameter
Name
Maximum Operating Frequency
Duty Cycle
[3, 5]
= t
2
÷
t
1
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Rising Edge Rate
[3]
Falling Edge Rate
[3]
Output to Output Skew
[3]
SDRAM Buffer LH Propogation
Delay
[3]
SDRAM Buffer HL Propogation
Delay
[3]
SDRAM Buffer Enable Delay
[3]
SDRAM Buffer Disable Delay
[3]
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
45.0
0.9
0.9
–250
1.0
1.0
1.0
1.0
3.5
3.5
5
20
50.0
1.5
1.5
Test Conditions
Min
Typ
Max
100
55.0
4.0
4.0
+250
5.0
5.0
12
30
Unit
MHz
%
V/ns
V/ns
ps
ns
ns
ns
ns
Switching Waveforms
Figure 2. Duty Cycle Timing
t
1
t
2
1.5V
1.5V
1.5V
Figure 3. All Outputs Rise/Fall Time
OUTPUT
2.4V
0.4V
t
3
2.4V
0.4V
t
4
3.3V
0V
Figure 4. Output-Output Skew
OUTPUT
1.5V
OUTPUT
t
5
1.5V
Notes
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns.
Document #: 38-07143 Rev. *B
Page 4 of 8
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CY2314ANZ
Switching Waveforms
(continued)
Figure 5. SDRAM Buffer LH and HL Propagataion Delay
INPUT
OUTPUT
t
6
t
7
Figure 6. SDRAM Buffer Enable and Disable Times
OE
Three-State
OUTPUTS
t
8
Active
t
9
Test Circuit
V
DD
0.1
μF
OUTPUTS
CLK out
C
LOAD
GND
Document #: 38-07143 Rev. *B
Page 5 of 8
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