CY2308
3.3V Zero Delay Buffer
Features
■
■
■
■
■
■
■
■
■
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
Multiple configurations, see
Available CY2308 Configurations
on page 3
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3V operation
Industrial temperature available
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table
Select Input Decoding
on page 2. If all output clocks are not required, Bank B is
three-stated. The input clock is directly applied to the output for
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 50
μA
of current draw. The PLL shuts down in two additional cases as
shown in the table
Select Input Decoding
on page 2.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table
Available CY2308 Configurations
on page 3. The
CY2308–1 is the base part where the output frequencies equal
the reference if there is no counter in the feedback path. The
CY2308–1H is the high drive version of the –1 and rise and fall
times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output
frequencies depend on the output that drives the feedback pin.
The CY2308–3 enables the user to obtain 4X and 2X frequencies
on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
Logic Block Diagram
/2
REF
PLL
MUX
FBK
CLKA1
CLKA2
/2
Extra Divider (–3, –4)
Extra Divider (–5H)
CLKA3
CLKA4
S2
S1
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
CLKB4
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 12, 2009
[+] Feedback
CY2308
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC (Top view)
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Table 1. Pin Definitions - 16 Pin SOIC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
[2]
CLKA2
[2]
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
GND
V
DD
CLKA3
[2]
CLKA4
[2]
FBK
Signal
Clock output, Bank A
Clock output, Bank A
3.3V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
Description
Input reference frequency, 5V tolerant input
Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Tri-State
Driven
Driven
[4]
Driven
CLOCK B1–B4
Tri-State
Tri-State
Driven
[4]
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
Document Number: 38-07146 Rev. *H
Page 2 of 15
[+] Feedback
CY2308
Available CY2308 Configurations
Device
CY2308–1
CY2308–1H
CY2308–2
CY2308–2
CY2308–3
CY2308–3
CY2308–4
CY2308–5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
Reference
Reference
Reference/2
Reference
Reference or Reference
[5]
2 X Reference
2 X Reference
Reference /2
Bank B Frequency
Zero Delay and Skew Control
Figure 2. REF. Input to CLKA/CLKB Delay Versus Difference in Loading between FBK Pin and CLKA/CLKB Pins
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the
Zero
Delay and Skew Control
graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Note
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
Document Number: 38-07146 Rev. *H
Page 3 of 15
[+] Feedback
CY2308
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except Ref) .............. –0.5V to V
DD
+ 0.5V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature .................................. –65°C to +150°C
Junction Temperature .................................................. 150°C
Static Discharge Voltage
(MIL-STD-883, Method 3015).................................... >2000V
Operating Conditions for Commercial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
[6]
Power up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
Description
Min
3.0
0
–
–
–
0.05
Max
3.6
70
30
15
7
50
Unit
V
°C
pF
pF
pF
ms
Electrical Characteristics for Commercial Temperature Devices
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
[7]
Output HIGH Voltage
[7]
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA (–1, –2, –3, –4)
I
OL
= 12 mA (–1H, –5H)
I
OH
= –8 mA (–1, –2, –3, –4)
I
OH
= –12 mA (–1H, –5H)
Unloaded outputs, 100 MHz REF,
Select inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF
(–1, –2, –3, –4)
Unloaded outputs, 33 MHz REF
(–1, –2, –3, –4)
Test Conditions
Min
–
2.0
–
–
–
2.4
–
–
–
–
–
Max
0.8
–
50.0
100.0
0.4
–
12.0
45.0
70.0
(–1H,–5H)
32.0
18.0
Unit
V
V
μA
μA
V
V
μA
mA
mA
mA
mA
Power Down Supply Current REF = 0 MHz
Supply Current
Switching Characteristics for Commercial Temperature Devices
Parameter
[8]
t
1
t
1
t
1
t
PD
t
PD
Name
Output Frequency
Output Frequency
Output Frequency
Duty Cycle
[7, 8]
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
Duty Cycle
[7, 8]
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
Test Conditions
30 pF load, All devices
20 pF load, –1H, –5H devices
[9]
15 pF load, –1, –2, –3, –4 devices
Measured at 1.4V, F
OUT
= 66.66 MHz
30 pF load
Measured at 1.4V, F
OUT
< 50 MHz
15 pF load
Min
10
10
10
40.0
45.0
Typ.
–
–
–
50.0
50.0
Max
100
133.3
133.3
60.0
55.0
Unit
MHz
MHz
MHz
%
%
Notes
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters are specified with loaded outputs.
9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
Document Number: 38-07146 Rev. *H
Page 4 of 15
[+] Feedback
CY2308
Switching Characteristics for Commercial Temperature Devices
(continued)
Parameter
[8]
t
3
t
3
t
3
t
4
t
4
t
4
t
5
Name
Rise Time
[7, 8]
(–1, –2, –3, –4)
Rise Time
[7, 8]
(–1, –2, –3, –4)
Rise Time
[7, 8]
(–1H, –5H)
Fall Time
[7, 8]
(–1, –2, –3, –4)
Fall Time
[7, 8]
(–1, –2, –3, –4)
Fall Time
[7, 8]
(–1H, –5H)
Output to Output Skew on
same Bank
(–1, –2, –3, –4)
[7, 8]
Test Conditions
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
All outputs equally loaded
Min
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
Max
2.20
1.50
1.50
2.20
1.50
1.25
200
Unit
ns
ns
ns
ns
ns
ns
ps
Output to Output Skew (–1H, All outputs equally loaded
–5H)
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
Output Bank A to Output
Bank B Skew (–2, –3)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to
FBK Rising Edge
[7, 8]
Device to Device Skew
[7, 8]
Output Slew Rate
[7, 8]
Cycle to Cycle Jitter
[7, 8]
(–1, –1H, –4, –5H)
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins
of devices
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2
Measured at 66.67 MHz, loaded
outputs,
15 pF load
Measured at 66.67 MHz, loaded
outputs,
30 pF load
Measured at 133.3 MHz, loaded
outputs,
15 pF load
t
J
Cycle to Cycle Jitter
[7, 8]
(–2, –3)
Measured at 66.67 MHz, loaded
outputs
30 pF load
Measured at 66.67 MHz, loaded
outputs
15 pF load
t
LOCK
PLL Lock Time
[7, 8]
Stable power supply, valid clocks
presented on REF and FBK pins
–
–
–
–
–
1
–
–
–
–
0
0
–
75
200
200
400
±250
700
ps
ps
ps
ps
ps
V/ns
200
ps
–
–
200
ps
–
–
100
ps
–
–
400
ps
–
–
400
ps
–
–
1.0
ms
Document Number: 38-07146 Rev. *H
Page 5 of 15
[+] Feedback
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
