One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
50 ps typical cycle-cycle jitter (15 pF, 66 MHz)
Test Mode to bypass phase locked loop (PLL) (CY2309C) only,
see
“Select Input Decoding for CY2309C”
on page 3
Available in space saving 16-pin 150 Mil SOIC or 4.4 mm
TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC
package (CY2305C)
3.3V operation
Commercial, Industrial and Automotive-A flows available
skew clocks. The -1H versions of each device operate up to
100-133 MHz frequencies and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the
“Select Input
Decoding for CY2309C”
on page 3. If all output clocks are not
required, BankB is three-stated. The input clock is directly
applied to the outputs by the select inputs for chip and system
testing purposes.
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0
μA
of current draw for commercial
temperature devices and 25.0
μA
for industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the
“Select Input Decoding for
CY2309C”
on page 3.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
The CY2305C or CY2309C is available in two or three different
configurations as shown in the
“Ordering Information”
on page 9.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
■
■
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
Logic Block Diagram for CY2305C
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document Number: 38-07672 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 27, 2008
[+] Feedback
CY2305C
CY2309C
Logic Block Diagram for CY2309C
PLL
REF
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
S2
Select Input
Decoding
S1
CLKB1
CLKB2
CLKB3
CLKB4
Pinouts
CY2305C
Figure 1. Pin Diagram - 8 Pin SOIC
Top View
REF
CLK2
CLK1
GND
1
2
3
4
CY2305C
8
7
6
5
CLKOUT
CLK4
V
DD
CLK3
Table 1. Pin Description - 8 Pin SOIC
Pin
1
2
3
4
5
6
7
8
REF
[1]
CLK2
[2]
CLK1
[2]
GND
CLK3
[2]
V
DD
CLK4
[2]
CLKOUT
[2]
Signal
Input reference frequency
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Document Number: 38-07672 Rev. *H
Page 2 of 12
[+] Feedback
CY2305C
CY2309C
CY2309C
Figure 2. Pin Diagram - 16 Pin SOIC/TSSOP
Top View
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CY2309C
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Table 2. Pin Definition - 16 Pin SOIC/TSSOP
Pin
Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
[2]
CLKA2
[2]
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
GND
V
DD
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
Input reference frequency
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Description
Buffered output, internal feedback on this pin
Table 3. Select Input Decoding for CY2309C
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three state
Driven
Driven
Driven
CLOCK B1–B4
Three state
Three state
Driven
Driven
CLKOUT
[4]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input or output delay.
For applications requiring zero input or output delay, all outputs including CLKOUT are equally loaded. Even if CLKOUT is not used,
it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay.
For zero output or output skew, all outputs are loaded equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers”.
Notes
3. Weak pull ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *H
Page 3 of 12
[+] Feedback
CY2305C
CY2309C
Absolute Maximum Conditions
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Input Voltage (Except REF) ............ –0.5V to V
DD
+ 0.5V
DC Input Voltage REF ........................... –0.5V to V
DD
+ 0.5V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature ................................................. 150°C
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