CY14C256PA
CY14B256PA
CY14E256PA
256-Kbit (32 K × 8) SPI nvSRAM
with Real Time Clock
256-Kbit (32 K × 8) SPI nvSRAM with Real Time Clock
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 32 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
❐
RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
❐
Automatic STORE on power-down with a small capacitor
■
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
Data retention: 20 years at 85C
■
Real time clock (RTC)
❐
Full-featured RTC
❐
Watchdog timer
❐
Clock alarm with programmable interrupts
❐
Backup power fail indication
❐
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
❐
Capacitor or battery backup for RTC
❐
Backup current of 0.45 µA (typical)
■
40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
❐
40 MHz clock rate SPI write and read with zero cycle delay
❐
104 MHz clock rate SPI write and read (with special fast read
instructions)
❐
Supports SPI mode 0 (0,0) and mode 3 (1,1)
■
SPI access to special functions
❐
Nonvolatile STORE/RECALL
❐
8-byte serial number
❐
Manufacturer ID and Product ID
❐
Sleep mode
■
■
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4, 1/2, or entire array
Low power consumption
❐
Average active current of 3 mA at 40 MHz operation
❐
Average standby mode current of 250
A
❐
Sleep mode current of 8
A
Industry standard configurations
❐
Operating voltages:
• CY14C256PA : V
CC
= 2.4 V to 2.6 V
• CY14B256PA : V
CC
= 2.7 V to 3.6 V
• CY14E256PA : V
CC
= 4.5 V to 5.5 V
❐
Industrial temperature
❐
16-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
■
■
Overview
The Cypress CY14X256PA combines a 256-Kbit nvSRAM
[1]
with
a full-featured RTC in a monolithic integrated circuit with serial
SPI interface. The memory is organized as 32 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Logic Block Diagram
V
CC
V
CAP
V
RTCcap
V
RTCbat
Serial Number
8x8
Manufacture ID/
Product ID
Power Control
Block
SLEEP
SI
CS
SCK
WP
SO
SPI Control Logic
Write Protection
Instruction decoder
QuantrumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
RDRTC/WRTC
WRSR/RDSR/WREN
Status Register
X
in
INT/SQW
X
out
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document #: 001-65281 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 4, 2011
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CY14C256PA
CY14B256PA
CY14E256PA
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 4
Software STORE Operation ........................................ 5
Hardware STORE and HSB pin Operation ................. 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power Up) ................................... 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 5
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ......................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power-On Reset .......................................................... 8
Power Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Fast Read Status Register (FAST_RDSR)
Instruction ......................................................................... 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 11
Write Enable (WREN) Instruction .............................. 11
Write Disable (WRDI) Instruction .............................. 12
Block Protection ........................................................ 12
Hardware Write Protection (WP Pin) ......................... 12
Memory Access .............................................................. 12
Read Sequence (READ) Instruction .......................... 12
Fast Read Sequence (FAST_READ) Instruction ...... 12
Write Sequence (WRITE) Instruction ........................ 13
RTC Access ..................................................................... 15
READ RTC (RDRTC) Instruction .............................. 15
Fast Read Sequence (FAST_RDRTC) Instruction .... 15
WRITE RTC (WRTC) Instruction ............................... 16
nvSRAM Special Instructions ........................................ 17
Software STORE (STORE) Instruction ..................... 17
Software RECALL (RECALL) Instruction .................. 17
AutoStore Enable (ASENB) Instruction ..................... 17
AutoStore Disable (ASDISB) Instruction ................... 17
Special Instructions ....................................................... 17
SLEEP Instruction ..................................................... 17
Serial Number ................................................................. 18
WRSN (Serial Number Write) Instruction .................. 18
RDSN (Serial Number Read) Instruction ................... 19
FAST_RDSN (Fast Serial Number Read)
Instruction ......................................................................... 19
Device ID ......................................................................... 20
RDID (Device ID Read) Instruction ........................... 20
FAST_RDID (Fast Device ID Read) Instruction ........ 21
HOLD Pin Operation ................................................. 21
Real Time Clock Operation ............................................ 22
nvTIME Operation ..................................................... 22
Clock Operations ....................................................... 22
Reading the Clock ..................................................... 22
Setting the Clock ....................................................... 22
Backup Power ........................................................... 22
Stopping and Starting the Oscillator .......................... 22
Calibrating the Clock ................................................. 23
Alarm ......................................................................... 23
Watchdog Timer ........................................................ 23
Programmable Square Wave Generator ................... 24
Power Monitor ........................................................... 24
Backup Power Monitor .............................................. 24
Interrupts ................................................................... 24
Interrupt Register ....................................................... 24
Flags Register ........................................................... 25
Best Practices ................................................................. 31
Maximum Ratings ........................................................... 32
DC Electrical Characteristics ........................................ 32
Data Retention and Endurance ..................................... 33
Capacitance .................................................................... 33
Thermal Resistance ........................................................ 33
AC Test Conditions ........................................................ 34
RTC Characteristics ....................................................... 35
AC Switching Characteristics ....................................... 35
AutoStore or Power-Up RECALL .................................. 37
Switching Waveforms .................................................... 37
Software Controlled STORE/RECALL Cycles .............. 38
Hardware STORE Cycle ................................................. 39
Ordering Information ...................................................... 40
Ordering Code Definitions ......................................... 40
Package Diagram ............................................................ 41
Acronyms ........................................................................ 42
Document Conventions ................................................. 42
Units of Measure ....................................................... 42
Document History Page ................................................. 43
Sales, Solutions, and Legal Information ...................... 44
Worldwide Sales and Design Support ....................... 44
Products .................................................................... 44
PSoC Solutions ......................................................... 44
Document #: 001-65281 Rev. *B
Page 2 of 44
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CY14C256PA
CY14B256PA
CY14E256PA
Pinout
Figure 1. Pin Diagram - 16-pin SOIC
NC
VRTCbat
Xout
Xin
WP
HOLD
V
RTCcap
V
SS
1
2
3
4
5
6
7
8
Top View
not to scale
16
15
14
13
12
11
10
9
V
CC
INT/SQW
V
CAP
SO
SI
SCK
CS
HSB
Pin Definitions
Pin Name
CS
SCK
SI
SO
WP
HOLD
HSB
I/O Type
Input
Input
Input
Output
Input
Input
Input/Output
Description
Chip select: Activates the device when pulled LOW. Driving this pin HIGH puts the device in low
power standby mode.
Serial clock: Runs at speeds up to a maximum of f
SCK
. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial input: Pin for input of all SPI instructions and data.
Serial output: Pin for output of data through SPI.
Write Protect: Implements hardware write protection in SPI.
HOLD pin: Suspends Serial Operation.
Hardware STORE Busy: Output: Indicates busy status of nvSRAM when LOW. After each
Hardware and Software STORE operation HSB is driven HIGH for a short time (t
HHHD
) with
standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external
pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
Capacitor backup for RTC: Left unconnected if V
RTCbat
is used.
Battery backup for RTC: Left unconnected if V
RTCcap
is used.
Crystal output connection
Crystal input connection
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the
watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or
LOW (open drain). In calibration mode, a 512 Hz square wave is driven out. In the square wave
mode, you may select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a
continuous output.
No connect. This pin is not connected to the die.
Ground
Power supply
V
CAP
Power supply
V
RTCcap
V
RTCbat
Xout
Xin
INT/SQW
Power supply
Power supply
Output
Input
Output
NC
V
SS
V
CC
No connect
Power supply
Power supply
Document #: 001-65281 Rev. *B
Page 3 of 44
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CY14C256PA
CY14B256PA
CY14E256PA
Device Operation
CY14X256PA is a 256-Kbit serial (SPI) nvSRAM memory with
integrated RTC and SPI interface. All the reads and writes to
nvSRAM happen to the SRAM, which gives nvSRAM the unique
capability to handle infinite writes to the memory. The data in
SRAM is secured by a STORE sequence that transfers the data
in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (V
CAP
) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
In CY14X256PA, the 256-Kbit memory array is organized as
32 K words × 8 bits. The memory can be accessed through a
standard SPI interface that enables very high clock speeds up to
40 MHz with zero cycle delay read and write cycles. This
nvSRAM chip also supports 104 MHz SPI access speed with a
special instruction for read operation. CY14X256PA supports
SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates
as SPI slave. The device is enabled using the Chip Select (CS)
pin and accessed through Serial Input (SI), Serial Output (SO),
and Serial Clock (SCK) pins.
CY14X256PA provides the feature for hardware and software
write protection through the WP pin and WRDI instruction.
CY14X256PA also provides mechanisms for block write
protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the
Status Register. Further, the HOLD pin is used to suspend any
serial communication without resetting the serial sequence.
CY14X256PA uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, CY14X256PA provides four special instructions that allow
access to four nvSRAM specific functions: STORE, RECALL,
AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and two bytes of address. The data
is read out on the SO pin.
Speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, two bytes of address, and one dummy
byte. The data is read out on the SO pin.
CY14X256PA enables burst mode reads to be performed
through SPI. This enables reads on consecutive addresses
without issuing a new READ instruction. When the last address
in memory is reached in burst mode read, the address rolls over
to 0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the Memory Access
section of SPI Protocol Description
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The CY14X256PA STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X256PA is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V
CAP
) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore
Disable (ASDISB) Instruction on page 17).
If
AutoStore is enabled without a capacitor on the V
CAP
pin, the
device attempts an AutoStore operation without sufficient charge
Page 4 of 44
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14X256PA allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
Document #: 001-65281 Rev. *B
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CY14C256PA
CY14B256PA
CY14E256PA
to complete the Store. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to
DC Electrical
Characteristics on page 32
for the size of the V
CAP
.
Figure 2. AutoStore Mode
V
CC
Note
For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. In CY14X256PA, a
RECALL may be initiated in two ways: Hardware RECALL,
initiated on power-up and Software RECALL, initiated by a SPI
RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
0.1uF
10kOhm
V
CC
CS
V
CAP
V
CAP
Hardware RECALL (Power Up)
During power-up, when V
CC
crosses V
SWITCH
, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power Up RECALL cycle takes t
FA
time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
V
SS
Software STORE Operation
Software STORE allows the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction regardless of whether or not a
write has been performed since the last NV operation.
A STORE cycle takes t
STORE
time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready/Busy status of the nvSRAM. After the t
STORE
cycle time
is completed, the SRAM is activated again for read and write
operations.
Software RECALL
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. In
CY14X256PA, this can be done by issuing a RECALL instruction
in SPI.
A Software RECALL takes t
RECALL
time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Hardware STORE and HSB pin Operation
The HSB pin in CY14X256PA is used to control and
acknowledge STORE operations. If no STORE/RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the CY14X256PA
conditionally initiates a STORE operation after t
DELAY
duration.
A STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for t
STORE
duration or as long
as HSB pin is LOW. The HSB pin also acts as an open drain
driver (internal 100 k weak pull-up resistor) that is internally
driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note
After each Hardware and Software STORE operation, HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by an internal 100 k pull-up
resistor.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled in CY14X256PA by using the ASDISB instruction. If
this is done, the nvSRAM does not perform a STORE operation
at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note
CY14X256PA comes from the factory with AutoStore
Enabled. If AutoStore is disabled and V
CAP
is not required, then
the V
CAP
pin must be left open. The V
CAP
pin must never be
connected to ground. The Power Up RECALL operation cannot
be disabled in any case.
Document #: 001-65281 Rev. *B
Page 5 of 44
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