CY14B104K, CY14B104M
4-Mbit (512 K × 8/256 K × 16) nvSRAM
with Real Time Clock
4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock
Features
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■
■
■
■
■
■
■
■
■
■
■
■
■
■
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Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Industrial temperature
44-pin and 54-pin thin small outline package (TSOP) Type II
Pb-free and restriction of hazardous substances (RoHS)
compliant
25 ns and 45 ns access times
Internally organized as 512 K × 8 (CY14B104K) or 256 K × 16
(CY14B104M)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap non-volatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM is initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Single 3 V +20%, –10% operation
Data integrity of Cypress nvSRAM combined with full-featured
real time clock (RTC)
Functional Description
The Cypress CY14B104K and CY14B104M combines a 4-Mbit
non-volatile static RAM (nvSRAM) with a full-featured RTC in a
monolithic integrated circuit. The embedded non-volatile
elements incorporate QuantumTrap technology producing the
world’s most reliable non-volatile memory. The SRAM is read
and written infinite number of times, while independent
non-volatile data resides in the non-volatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
V
CC
V
CA
P
Logic Block Diagram
[1, 2, 3]
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
I
N
P
U
T
B
U
F
F
E
R
S
R
O
W
D
E
C
O
D
E
R
Quatrum
Trap
2048 X 2048
STORE
RECALL
STATIC RAM
ARRAY
2048 X 2048
POWER
CONTROL
V
RTCbat
V
RTCcap
STORE/RECALL
CONTROL
HSB
SOFTWARE
DETECT
A
14
- A
2
RTC
X
out
X
in
INT
COLUMN I/O
MUX
A
18
- A
0
OE
COLUMN DEC
WE
CE
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BLE
BHE
Notes
1. Address A
0
–A
18
for × 8 configuration and Address A
0
–A
17
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07103 Rev. *U
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 12, 2011
[+] Feedback
CY14B104K, CY14B104M
Contents
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE (HSB) Operation ................................. 5
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 7
Noise Considerations ....................................................... 7
Real Time Clock Operation .............................................. 7
nvTIME Operation ....................................................... 7
Clock Operations ......................................................... 7
Reading the Clock ....................................................... 7
Setting the Clock ......................................................... 7
Backup Power ............................................................. 7
Stopping and Starting the Oscillator ............................ 8
Calibrating the Clock ................................................... 8
Alarm ........................................................................... 8
Watchdog Timer .......................................................... 8
Power Monitor ............................................................. 9
Interrupts ..................................................................... 9
Flags Register ........................................................... 10
Best Practices ................................................................. 15
Maximum Ratings ........................................................... 16
Operating Range ............................................................. 16
DC Electrical Characteristics ........................................ 16
Data Retention and Endurance ..................................... 17
Capacitance .................................................................... 17
Thermal Resistance ........................................................ 17
AC Test Loads ................................................................ 17
AC Test Conditions ........................................................ 17
RTC Characteristics ....................................................... 18
AC Switching Characteristics ....................................... 19
SRAM Read Cycle .................................................... 19
SRAM Write Cycle ..................................................... 19
AutoStore/Power-Up RECALL ....................................... 22
Switching Waveforms .................................................... 22
Software Controlled STORE and RECALL Cycle ........ 23
Hardware STORE Cycle ................................................. 24
Truth Table For SRAM Operations ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ............................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 35
Worldwide Sales and Design Support ....................... 35
Products .................................................................... 35
PSoC Solutions ......................................................... 35
Document #: 001-07103 Rev. *U
Page 2 of 35
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CY14B104K, CY14B104M
Pinouts
Figure 1. Pin Diagram – 44-pin and 54-pin TSOP II
INT
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
WE
A
5
A
6
A
7
A
8
A
9
X
out
X
in
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[4]
NC
A
18
A
17
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ5
DQ4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
INT
[5]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
[4]
NC
A
17
A
16
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
44-pin TSOP II
(x 8)
54-pin TSOP II
(x 16)
Top View
(not to scale)
Top View
(not to scale)
X
out
X
in
V
RTCcap
V
RTCbat
Pin Definitions
Pin Name
A
0
– A
18
A
0
– A
17
DQ
0
– DQ
15
I/O Type
Input
Description
Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 262,144 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
DQ
0
– DQ
7
Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
NC
WE
CE
OE
BHE
BLE
X
out
X
in
V
RTCcap
V
RTCbat
INT
No connect
Input
Input
Input
Input
Input
Output
Input
No connects. This pin is not connected to the die.
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
Byte High Enable, Active LOW. Controls DQ
15
–DQ
8
.
Byte Low Enable, Active LOW. Controls DQ
7
–DQ
0
.
Crystal connection. Drives crystal on startup.
Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if V
RTCbat
is used.
Power supply Battery supplied backup RTC supply voltage. Left unconnected if V
RTCcap
is used.
Output
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor.
Also programmable to either active HIGH (push or pull) or LOW (open drain).
Notes
4. Address expansion for 8-Mbit. NC pin not connected to die.
5. Address expansion for 16-Mbit. NC pin not connected to die.
Document #: 001-07103 Rev. *U
Page 3 of 35
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CY14B104K, CY14B104M
Pin Definitions
(continued)
Pin Name
V
SS
V
CC
HSB
I/O Type
Ground
Description
Ground for the device. Must be connected to ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (t
HHHD
) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
V
CAP
Device Operation
The CY14B104K/CY14B104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a non-volatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the non-volatile cell (the
STORE operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. See
Truth Table For SRAM Operations on page 25
for a complete description of read and write modes.
AutoStore Operation
The CY14B104K/CY14B104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
AutoStore on page 6.
In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
V
CC
SRAM Read
The CY14B104K/CY14B104M performs a read cycle when CE
and OE are LOW, and WE and HSB are HIGH. The address
specified on pins A
0–18
or A
0–17
determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
t
AA
access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1 uF
10 kOhm
V
CC
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DO
0–15
are written into the memory if it is valid t
SD
before the end of a
WE controlled write or before the end of an CE controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers t
HZWE
after WE goes LOW.
WE
V
CAP
V
CAP
V
SS
Figure 2 on page 4
shows the proper connection of the storage
capacitor (V
CAP
) for automatic STORE operation. Refer to
DC
Electrical Characteristics on page 16
for the size of the V
CAP
. The
voltage on the V
CAP
pin is driven to V
CC
by a regulator on the
Page 4 of 35
Document #: 001-07103 Rev. *U
[+] Feedback
CY14B104K, CY14B104M
chip. A pull-up should be placed on WE to hold it inactive during
power-up. This pull-up is effective only if the WE signal is tristate
during power-up. Many MPUs tristate their controls on power-up.
This should be verified when using the pull-up. When the
nvSRAM comes out of power-on-RECALL, the MPU must be
active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile STOREs, AutoStore, and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by a software address sequence. The CY14B104K/CY14B104M
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiate, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place. To initiate the Software
STORE cycle, the following read sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the t
STORE
cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104K/CY14B104M conditionally initiates a
STORE operation after t
DELAY
. An actual STORE cycle begins
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (t
DELAY
) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104K/CY14B104M. But any SRAM read and
write cycles are inhibited until HSB is returned HIGH by MPU or
other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B104K/CY14B104M continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(V
CC
< V
SWITCH
), an internal RECALL request is latched. When
V
CC
again exceeds the V
SWITCH
on powerup, a RECALL cycle
is automatically initiated and takes t
HRECALL
to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Document #: 001-07103 Rev. *U
Page 5 of 35
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