CY14B101KA
CY14B101MA
1-Mbit (128 K × 8/64 K × 16) nvSRAM with
Real Time Clock
1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
❐
25 ns and 45 ns access times
❐
Internally organized as 128 K × 8 (CY14B101KA) or
64 K × 16 (CY14B101MA)
❐
Hands off automatic STORE on power-down with only a small
capacitor
❐
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
❐
RECALL to SRAM initiated on power-up or by software
■
High reliability
❐
Infinite Read, Write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
20 year data retention
■
Real time clock (RTC)
❐
Full featured real time clock
❐
Watchdog timer
❐
Clock alarm with programmable interrupts
❐
Capacitor or battery backup for RTC
❐
Backup current of 0.35 µA (Typ)
■
■
Industry standard configurations
❐
Single 3 V +20%, –10% operation
❐
Industrial temperature
Packages
❐
44-/54-pin thin small outline package (TSOP) Type II
❐
48-pin shrink small outline package (SSOP)
Pb-free and restriction of hazardous substances (RoHS)
compliant
■
■
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit
nvSRAM with a full featured real time clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM is read and written
an infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
V
CC
V
CA
P
Logic Block Diagram
[1, 2, 3]
Quatrum
Trap
1024 X 1024
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
R
O
W
D
E
C
O
D
E
R
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
POWER
CONTROL
V
RTCbat
V
RTCcap
STORE/RECALL
CONTROL
HSB
SOFTWARE
DETECT
A
14
- A
2
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
A
0
A
1
A
2
A
3
A
4
A
10
A
11
CE
BLE
I
N
P
U
T
B
U
F
F
E
R
S
RTC
X
out
X
in
INT
COLUMN I/O
MUX
A
16
- A
0
OE
COLUMN DEC
WE
BHE
Notes
1. Address A
0
–A
16
for × 8 configuration and Address A
0
–A
15
for × 16 configuration.
2. Data DQ
0
–DQ
7
for × 8 configuration and Data DQ
0
–DQ
15
for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-42880 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 22, 2011
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CY14B101KA
CY14B101MA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
SRAM Read ....................................................................... 5
SRAM Write ....................................................................... 5
AutoStore Operation ........................................................ 5
Hardware STORE (HSB) Operation ................................. 5
Hardware RECALL (Power-Up) ....................................... 6
Software STORE ............................................................... 6
Software RECALL ............................................................. 6
Preventing AutoStore ....................................................... 7
Data Protection ................................................................. 8
Noise Considerations ....................................................... 8
Real Time Clock Operation .............................................. 8
nvTIME Operation ....................................................... 8
Clock Operations ......................................................... 8
Reading the Clock ....................................................... 8
Setting the Clock ......................................................... 8
Backup Power ............................................................. 8
Stopping and Starting the Oscillator ............................ 9
Calibrating the Clock ................................................... 9
Alarm ........................................................................... 9
Watchdog Timer .......................................................... 9
Power Monitor ........................................................... 10
Interrupts ................................................................... 10
Flags Register ........................................................... 11
Best Practices ................................................................. 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
DC Electrical Characteristics ........................................ 17
Data Retention and Endurance ..................................... 18
Capacitance .................................................................... 18
Thermal Resistance ........................................................ 18
AC Test Loads ................................................................ 18
AC Test Conditions ........................................................ 18
RTC Characteristics ....................................................... 19
AC Switching Characteristics ....................................... 20
SRAM Read Cycle .................................................... 20
SRAM Write Cycle ..................................................... 20
Switching Waveforms .................................................... 20
AutoStore/Power-Up RECALL ....................................... 23
Switching Waveforms .................................................... 23
Software Controlled STORE/RECALL Cycle ................ 24
Switching Waveforms .................................................... 24
Hardware STORE Cycle ................................................. 25
Switching Waveforms .................................................... 25
Truth Table For SRAM Operations ................................ 26
Ordering Information ...................................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ............................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Document #: 001-42880 Rev. *I
Page 2 of 34
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CY14B101KA
CY14B101MA
Pinouts
Figure 1. Pin Diagram – 44-pin, 54-pin TSOP II, and 48-pin SSOP
INT 1
[7]
NC
2
A
0
3
A
1
4
A
2
5
A
3
6
A
4
7
CE 8
DQ
0
9
DQ
1
10
V
CC
11
12
V
SS
DQ
2
13
DQ
3
14
WE 15
A
5
16
A
6
17
A
7
18
A
8
19
A
9
20
Xout
21
Xin
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
HSB
NC
[6]
NC
[5]
NC
[4]
NC
A
16
A
15
OE
DQ
7
DQ
6
V
SS
V
CC
DQ5
DQ4
V
CAP
A
14
A
13
A
12
A
11
A
10
V
RTCcap
V
RTCbat
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
INT
A
4
NC
NC
NC
V
SS
NC
V
RTCbat
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
Xout
Xin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
WE
A
13
A
8
A
9
NC
A
11
NC
NC
NC
V
SS
NC
V
RTCcap
DQ6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
INT
[7]
NC
A
0
A
1
A
2
A
3
A
4
CE
DQ
0
DQ
1
DQ
2
DQ
3
V
CC
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
WE
A
5
A
6
A
7
A
8
A
9
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
[6]
NC
[5]
NC
[4]
NC
A
15
OE
BHE
BLE
DQ
15
DQ
14
DQ
13
DQ
12
V
SS
V
CC
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
A
14
A
13
A
12
A
11
A
10
NC
44-pin TSOP II
(× 8)
48-
pin
SSOP
(
×
8)
54-
pin
TSOP II
(
×
16)
Top View
(not to scale)
Top View
(not to scale)
Top View
(not to scale)
Xout
Xin
V
RTCcap
V
RTCbat
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
Document #: 001-42880 Rev. *I
Page 3 of 34
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CY14B101KA
CY14B101MA
Pin Definitions
Pin Name
A
0
–A
16
A
0
–A
15
DQ
0
–DQ
7
DQ
0
–DQ
15
NC
WE
CE
OE
BHE
BLE
X
out
X
in
V
RTCcap
V
RTCbat
INT
V
SS
V
CC
HSB
I/O Type
Input
Input/Output
No connect
Input
Input
Input
Input
Input
Output
Input
Description
Address inputs. Used to select one of the 131,072 Bytes of the nvSRAM for × 8 configuration.
Address inputs. Used to select one of the 65,536 Words of the nvSRAM for × 16 configuration.
Bidirectional data I/O Lines for × 8 configuration. Used as input or output lines depending on operation.
Bidirectional data I/O Lines for × 16 configuration. Used as input or output lines depending on operation.
No connects. This pin is not connected to the die.
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
Byte High Enable, Active LOW. Controls DQ
15
–DQ
8
.
Byte Low Enable, Active LOW. Controls DQ
7
–DQ
0
.
Crystal connection. Drives crystal on start up.
Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if V
RTCbat
is used.
Power supply Battery supplied backup RTC supply voltage. Left unconnected if V
RTCcap
is used.
Output
Ground
Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for short time (t
HHHD
) with standard output high
current and then weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
V
CAP
Document #: 001-42880 Rev. *I
Page 4 of 34
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CY14B101KA
CY14B101MA
Device Operation
The CY14B101KA/CY14B101MA nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B101KA/CY14B101MA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. Refer
Truth Table For SRAM Operations on page 26
for a complete description of read and write modes.
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Note
If the capacitor is not connected to V
CAP
pin, AutoStore
must be disabled using the soft sequence specified in
Preventing
AutoStore on page 7.
In case AutoStore is enabled without a
capacitor on V
CAP
pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 2. AutoStore Mode
V
CC
0.1 uF
10 kOhm
V
CC
SRAM Read
The CY14B101KA/CY14B101MA performs a read cycle
whenever CE and OE are LOW, and WE and HSB are HIGH.
The address specified on pins A
0–16
or A
0–15
determines which
of the 131,072 data bytes or 65,536 words of 16 bits each are
accessed. Byte enables (BHE, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the outputs are valid after a
delay of t
AA
(read cycle #1). If the read is initiated by CE or OE,
the outputs are valid at t
ACE
or at t
DOE
, whichever is later (read
cycle #2). The data output repeatedly responds to address
changes within the t
AA
access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
WE
V
CAP
V
CAP
V
SS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins IO
0–7
are
written into the memory if it is valid t
SD
before the end of a
WE-controlled write, or before the end of an CE-controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. It is recommended that OE
be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers t
HZWE
after WE goes LOW.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic STORE operation. Refer to
DC Electrical
Characteristics on page 17
for the size of the V
CAP
. The voltage
on the V
CAP
pin is driven to V
CC
by a regulator on the chip. A
pull-up should be placed on WE to hold it inactive during
power-up. This pull-up is only effective if the WE signal is tristate
during power-up. Many MPUs tristate their controls on power-up.
This should be verified when using the pull-up. When the
nvSRAM comes out of power-on-RECALL, the MPU must be
active or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
AutoStore Operation
The CY14B101KA/CY14B101MA stores data to the nvSRAM
using one of three storage operations. These three operations
are: Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device
power-down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B101KA/CY14B101MA.
During a normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
Hardware STORE (HSB) Operation
The CY14B101KA/CY14B101MA provides the HSB pin to
control and acknowledge the STORE operations. The HSB pin
is used to request a Hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B101KA/CY14B101MA conditionally
initiates a STORE operation after t
DELAY
. An actual STORE cycle
begins only if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
Document #: 001-42880 Rev. *I
Page 5 of 34
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