Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES
•
Wide supply voltage range from 1.65 to 3.6 V
•
Complies with JEDEC standards:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
•
3.6 V tolerant inputs and outputs
•
CMOS low power consumption
•
Direct interface with TTL levels (2.7 to 3.6 V)
•
Power-down mode
•
Latch-up performance exceeds 250 mA
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC573 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay input Dn to output Qn
CONDITIONS
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
74ALVC573
The 74ALVC573 is an octal D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all
internal latches.
The 74ALVC573 consists of eight D-type transparent
latches with 3-state true outputs. When LE is HIGH, data
at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state
each time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74ALVC573 is functionally identical to the
74ALVC373, but the has a different pin arrangement.
TYPICAL
2.5
ns
ns
ns
ns
UNIT
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
2.0
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
2.3
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
2.2
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
V
CC
= 3.3 V; notes and 1
outputs enabled
outputs disabled
Notes
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
1. The condition is V
I
= GND to V
CC
.
37
7
3.5
pF
pF
pF
2003 Jun 25
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE
See note 1
INPUT
OPERATING MODES
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
Note
1. H = HIGH voltage level;
a) h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
b) L = LOW voltage level;
c) l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
d) Z = high-impedance OFF-state.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74ALVC573D
74ALVC573PW
74ALVC573BQ
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
SYMBOL
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
DESCRIPTION
output enable input (active
LOW)
data input
data input
data input
data input
data input
data input
data input
data input
ground (0 V)
TEMPERATURE
RANGE
−40
to +85
°C
−40
to +85
°C
−40
to +85
°C
PINS
20
20
20
PACKAGE
SO20
TSSOP20
DHVQFN20
L
L
L
L
H
H
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
74ALVC573
INTERNAL
LATCH
L
H
L
H
L
H
OUTPUT
Qn
L
H
L
H
Z
Z
MATERIAL
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT764-1
PIN
11
12
13
14
15
16
17
18
19
20
SYMBOL
LE
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
V
CC
DESCRIPTION
latch enable input (active
HIGH)
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
3-state latch output
supply voltage
2003 Jun 25
3
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