TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
512K x 8 SRAM MODULE
SYS8512FK-20/25/35/45
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997
Issue 5.0 : November 1999
Description
The SYS8512FK is plastic 4M Static RAM Module
housed in a standard 32 pin Dual-In-Line package
organised as 512K x 8. The module utilises fast
256Kx4 SRAMs housed in SOJ packages, and
uses double sided surface mount techniques to
achieve a very high density module.
The module has Chip Select, Write Enable and
Output Enable control inputs; the Output Enable
pin allows faster access times than address access
during a Read Cycle.
Features
•
•
•
•
Access Times of 20/25/35/45 ns.
32 Pin 0.6" Dual-In-Line package with
JEDEC compatible pinout.
5 Volt Supply ± 10%.
Low Power Dissipation:
Average (min cycle)
2.42W (maximum).
Standby -L (CMOS)
44mW (maximum).
Completely Static Operation.
Equal Access and Cycle Times.
All Inputs and Outputs Directly TTL Compatible
On-board Supply Decoupling Capacitors.
•
•
•
•
Block Diagram
A0 - A17
D0 - D7
WE
OE
Pin Definition
256K X 4
SRAM
CS
256K X 4
SRAM
CS
256K X 4
SRAM
CS
256K X 4
SRAM
CS
CS
A18
DECODER
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Power (+5V)
Ground
A0 - A18
D0 - D7
CS
WE
OE
V
CC
GND
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
Package Details
Plastic 32 pin 0.6" Jedec DIP
TOP VIEW
ISSUE 5.0 November 1999
SYS8512FK-20/25/35/45
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.3
-
-55
Typ
-
2.5
-
Max
7.0
-
125
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -2.0V pulse of less than 10ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.3
0.8
70
85
Unit
V
V
V
o
C
o
C
(Commercial)
(Industrial)
DC Electrical Characteristics
(V
CC
=5V±10%)
Parameter
I/P Leakage Current
T
A
0 to 70
o
C
Min Typ
-8
-40
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
max
8
40
440
246
60
8
0.4
-
Unit
µA
µA
mA
mA
mA
mA
V
V
Symbol Test Condition
Address,OE,WE
I
LI
I
LO
I
CC1
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min. Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Output Leakage Current
Operating Supply Current
Standby Supply Current
TTL levels
CMOS levels
-L Version (CMOS)
I
SB1
I
SB2
I
SB3
V
OL
V
OH
Output Voltage
Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Parameter
Input Capacitance
(Address,OE,WE)
I/P Capacitance
(other)
I/O Capacitance
C
IN1
C
IN2
C
I/O
Note: Capacitance calculated, not measured.
Symbol Test Condition
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
32
8
32
Unit
pF
pF
pF
2
SYS8512FK-20/25/35/45
ISSUE 5.0 November 1999
AC Test Conditions
Output Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
H
L
H
WE
X
H
L
L
H
DATA PINS
High Impedance
Data Out
Data In
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
, I
SB3
I
CC1
I
CC1
I
CC1
I
SB1
, I
SB2
, I
SB3
MODE
Standby
Read
Write
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Low V
cc
Data Retention Characteristics - L Version Only
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Symbol
V
DR
I
CCDR2
t
CDR
t
R
Test Condition
CS > V
CC
-0.2V
V
CC
= 3.0V, CS > V
CC
-0.2V
T
OP
= 0 to 70
O
C
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
(1)
-
-
-
-
max
-
2
-
-
Unit
V
mA
ns
ms
Operation Recovery Time
Notes
(1) Typical figures are measured at 25°C.
(2) This parameter is guaranteed not tested.
3
ISSUE 5.0 November 1999
SYS8512FK-20/25/35/45
AC OPERATING CONDITIONS
Read Cycle
-20
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
20
-
-
-
3
0
0
0
0
max
-
20
20
10
-
-
-
12
10
-25
min
25
-
-
-
3
0
0
0
0
max
-
25
25
13
-
-
-
15
12
-35
min
35
-
-
-
3
0
0
0
0
max
-
35
35
15
-
-
-
15
20
-45
min
45
-
-
-
3
0
0
0
0
max
-
45
45
20
-
-
-
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
-20
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
20
17
17
0
15
3
0
12
0
0
max
-
-
-
-
-
-
12
-
-
-
min
25
20
20
0
20
3
0
15
0
0
-25
max
-
-
-
-
-
-
15
-
-
-
min
35
30
30
0
30
3
0
20
0
0
-35
max
-
-
-
-
-
-
15
-
-
-
min
45
40
40
0
30
3
0
25
0
0
-45
max
-
-
-
-
-
-
15
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
SYS8512FK-20/25/35/45
ISSUE 5.0 November 1999
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
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