MK2049-10
Communications Clock PLL
G
ENERAL
D
ESCRIPTION
The MK2049-10 is designed to serve as a pin
compatible, performance-improved replacement for the
MK2049-01. For full pin compatibility when using the
19.44 MHz / 38.88 MHz output selection please refer to
the MK2049-11.
The MK2049-10 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that produces a pin
selectable set of common telecommunications
reference frequencies. The output clock is phase
locked to an 8kHz (frame rate) input reference clock.
P
IN
A
SSIGNMENT
FS 1
X2
X1
VDD
VDD
VDD
GND
C LK 2
C LK 1
8K
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS 0
NC
CAP2
GND
CAP1
VDD
GND
IC LK
FS 3
FS 2
Features
•
•
•
•
•
•
Pin compatible upgrade for the MK2049-01
Single 5V power supply
20 pin SOIC package
Industrial temperature range
VCXO-based clock generator
Configurable jitter attenuation characteristics,
excellent for use as a Stratum source de-jitter circuit
For new 3.3V logic applications, please refer to the
following products:
MK2049-34/35/36
MK2058-01
MK2059-01
MK2069-01/02/03/04
Block Diagram
C
2
C
1
R
Z
C
L
C
L
O ptional C rystal Load C aps
E xtern al P u llab le C rystal
CAP2
C A P1 X 1
X2
IC LK
Referen ce
D ivid er
(used in buffer
m ode only)
P hase
D etector
V CX O
Charge
P um p
R eference
D ivid er
VCO
O u tp u t
D ivid er
D ivid e
by 2
C L K2
C L K1
VCXO
PLL
F eed b ack
D ivid er (N )
F eed b ack
Divid er
Tran slato r
PL L
8k
4
F S 3:0
D ivid er V alu e
L o o k-u p Tab le
MDS 2049-10 E
Integrated Circuit Systems, Inc.
q
1
525 Race Street San Jose, CA 95126
q
Revision 021402
tel (408) 295-9800
q
www.icst.com
MK2049-10
Communications Clock PLL
O
UTPUT
F
REQUENCY
S
ELECTION
T
ABLE
Input
Clock
(ICLK)
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
1.544 MHz
2.048 MHz
44.736 MHz
34.368 MHz
8 kHz
8 kHz
19-28 MHz
10-14 MHz
Input Selection
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Clocks
CLK1
CLK2
(MHz)
(MHz)
1.544
3.088
2.048
4.096
22.368
44.736
17.184
34.368
19.44
38.88
16.384
32.768
24.576
49.152
25.92
51.84
1.544
3.088
2.048
4.096
22.368
44.736
17.184
34.368
10.24
20.48
4.096
8.192
ICLK/2
ICLK
2x ICLK
4x ICLK
8K
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
n/a
n/a
n/a
n/a
8 kHz
8 kHz
n/a
n/a
Crystal
Freq
(MHz)
12.352
12.288
11.184
11.456
12.96
8.192
12.288
12.96
12.352
12.288
11.184
11.456
10.24
12.288
ICLK/2
ICLK
Notes
1
1
1
1
2
1
1
1
1
Note 1: These output frequency selections provide full pin compatibility with the ICS2049-01. Please note that the
external crystal frequency must be changed. Please review the external component values as well (see
recommendations table on page 6).
Note 2: This output frequency combination is also provided by the MK2049-01, however the MK2049-10 does not
provide full pin compatibility with this selection (an alternate input is selection is required). For full pin
compatibility with this output frequency combination, please refer to the MK2049-11.
MDS 2049-10 E
Integrated Circuit Systems, Inc.
q
2
525 Race Street San Jose, CA 95126
q
Revision 021402
tel (408) 295-9800
q
www.icst.com
MK2049-10
Communications Clock PLL
Pin Descriptions
Pin
Number
1
Pin
Name
FS1
Pin
Type
Input
Pin Description
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
Crystal Output. Connect this pin to the external reference crystal.
Crystal Input. Connect this pin to the external reference crystal.
Power Supply. Connect to +5V.
Power Supply. Connect to +5V.
Power Supply. Connect to +5V.
Ground.
Clock output, frequency determined by status of FS3:0 per table on
page 2.
Clock output, frequency determined by status of FS3:0 per table on
page 2.
8.000kHz Clock Output, applicable modes only, refer to table on page 2.
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
Input Clock Connection.
Ground.
Power Supply. Connect to +5V.
Loop Filter Connection. Refer to Block Diagram on page 1.
Ground.
Loop Filter Connection. Refer to Block Diagram on page 1.
No internal connection. This pin should be connected to ground to
minimize noise coupling into pin CAP2.
Frequency selection input. Determines output clock frequencies per
table on page 2. Internal pull-up, will assume logic high when
unconnected.
2
3
4
5
6
7
8
9
10
11
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8k
FS2
-
-
Power
Power
Power
Power
Output
Output
Output
Input
12
FS3
Input
13
14
15
16
17
18
19
20
ICLK
GND
VDD
CAP1
GND
CAP2
NC
FS0
Input
Power
Power
-
Power
-
-
Input
MDS 2049-10 E
Integrated Circuit Systems, Inc.
q
3
525 Race Street San Jose, CA 95126
q
Revision 021402
tel (408) 295-9800
q
www.icst.com
MK2049-10
Communications Clock PLL
Functional Description
The MK2049-10 is a PLL (Phased Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock. It contains
two cascaded PLL’s with table selected divider ratios.
The first PLL is VCXO-based and uses an external
pullable crystal as part of the normal “VCO” (voltage
controlled oscillator) function of the PLL. The use of a
VCXO assures a low phase noise clock source even
when a low PLL loop bandwidth is implemented. A low
loop bandwidth is needed when the input reference
frequency at the phase detector is low, or when jitter
attenuation of the input reference is desired.
The second PLL is used to translate or multiply the
frequency of the VCXO PLL. The Translator PLL uses
an on-chip VCO for output clock generation and is
configured with high loop bandwidth.
The divide values of the divider blocks within both PLLs
are set through table selection.
External components are used to configure the VCXO
PLL loop response. This serves to maximize loop
stability and to achieve the desired input clock jitter
attenuation characteristics.
Setting the VCXO PLL Loop Response.
The VCXO PLL loop response is determined both by
fixed device characteristics and by other characteristics
set by the user. This includes the values of R
Z
, C
1
, and
C
2
as shown in the Block Diagram on page 1.
The VCXO PLL loop bandwidth is approximated by:
R
Z
×
I
CP
×
K
O
-
NBW(VCXO PLL)
= ---------------------------------
2π
×
N
Where:
R
Z
= Value of resistor R
Z
in loop filter in Ohms
I
CP
= Charge pump current in amps = 50
µA
(fixed, not adjustable)
K
O
= VCXO Gain in Hz/V
(see table on page 8)
N = XTAL frequency / input clock frequency
(see 4th column of table on page 6)
The above equation calculates the “normalized” loop
bandwidth (denoted as “NBW”) which is approximately
equal to the - 3dB bandwidth. NBW does not take into
account the effects of damping factor or the second
pole imposed by C
2
. It does, however, provide a useful
approximation of filter performance.
To prevent jitter on the output clocks due to modulation
of the VCXO PLL by the phase detector frequency, the
following general rule should be observed:
NBW(VCXO PLL)
≤
.
Application Information
The MK2049-10 is a mixed analog / digital integrated
circuit that is sensitive to PCB (printed circuit board)
layout and external component selection. Used
properly, the device will provide the same high
performance expected from a canned VCXO-based
hybrid timing device, but at a lower cost. To help avoid
unexpected problems, the guidance provided in the
sections below should be followed.
f(Input Frequency)
----------------------------------------
20
The PLL loop damping factor is determined by:
R
Z
I
CP
×
C
1
×
K
O
DF(VCLK) = -----
×
---------------------------------
-
2
N
Where:
C
1
= Value of capacitor C
1
in loop filter in
Farads
In general, the loop damping factor should be 0.7 or
greater to ensure output stability. A higher damping
factor will create less peaking in the passband and will
further assure output stability with the presence of
system and power supply noise. A damping factor of 4
or greater will assure a passband peak less then 0.2dB
MDS 2049-10 E
Integrated Circuit Systems, Inc.
q
4
525 Race Street San Jose, CA 95126
q
Revision 021402
tel (408) 295-9800
q
www.icst.com
MK2049-10
Communications Clock PLL
(see also notes below regarding C
2
) which may be
required for network clock wander transfer compliance.
A high damping factor may also increase output clock
jitter when there is excess digital noise in the system
application, due to the reduced ability of the PLL to
respond to and therefore compensate for phase noise
ingress.
Loop Filter Response Software
ICS has a PC-based program available that simulates
VCXO PLL loop response characteristics. This can be
used instead of the above bandwidth and damping
factor equations. The user enters external loop filter
component values and other listed device
characteristics. The program generates a PLL
frequency response graph, which translates to jitter
attenuation characteristics. Normalized bandwidth
(NBW) and damping factor values are also calculated.
To obtain this free software please contact the
applications department of ICS, MicroClock Division, at
(408) 297-1201.
Notes on setting the value of C
2
As another general rule, the following relationship
should be maintained between components C1 and C2
in the loop filter:
C
1
-
C
2
= -----
20
C
2
establishes a second pole in the VCXO PLL loop
filter. For higher damping factors (> 1), calculate the
value of C
2
based on a C
1
value that would be used for
a damping factor of 1. This will prevent excessive
baseband peaking and loop instability that can lead to
output jitter.
C
2
also dampens VCXO input voltage modulation by
the charge pump correction pulses. A C
2
value that is
too low will result in increased output phase noise at
the phase detector frequency due to this. In extreme
cases where input jitter is high, charge pump current is
high, and C
2
is too small, the VCXO input voltage can
hit the supply or ground rail resulting in non-linear loop
response.
The best way to set the value of C
2
is to use the filter
response software available from ICS (please refer to
the following section). C
2
should be increased in value
until it just starts affecting the passband peak.
VCXO Gain (K
O
) vs. XTAL Frequency
6000
V C X O G ain (K
O
), H z per V o lt
5000
4000
3000
2000
1000
10
15
20
25
30
C rystal Frequ en cy, M H z
MDS 2049-10 E
Integrated Circuit Systems, Inc.
q
5
525 Race Street San Jose, CA 95126
q
Revision 021402
tel (408) 295-9800
q
www.icst.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
