ic power-down feature, reducing the power consumption by
over 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
one (CE
1
) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able one (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The WCMA1008U1X is available in a 32 Lead TSOP and
STSOP packages.
Functional Description
The WCMA1008U1X is a high-performance CMOS static
RAM organized as 128K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE
1
), an ac-
tive HIGH Chip Enable (CE
2
), an active LOW Output Enable
(OE) and three-state drivers. These devices have an automat-
Logic Block Diagram
Pin Configurations
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
25
26
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
STSOP
Top View
(not to scale)
INPUT BUFFER
I/O
0
I/O
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x 256x 8
ARRAY
CE
1
CE
2
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
WCMA1008U1X
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Supply Voltage to Ground Potential..... ..........–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
........................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
..................................–0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................20 mA
Static Discharge Voltage ..........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................>200 mA
Operating Range
Product
WCMA1008U1X
Range
Industrial
Ambient Temperature
–40°C to +85°C
V
CC
2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial)
Product
Min.
WCMA1008U1X
2.7V
V
CC
Range
Typ.
[2]
Speed
Max.
3.6V
70 ns
55 ns
Operating, I
CC
f = f
max
Typ.
[2]
Standby (I
SB2
)
Typ.
[2]
0.4
µA
Max.
30
µA
Max.
40 mA
3.0V
20 mA
Notes:
1. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
WCMA1008U1X
Electrical Characteristics
Over the Operating Range
WCMA1008U1X-70/55
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Cur-
rent
Output Leakage Cur-
rent
V
CC
Operating Supply
Current
Automatic CE
Power-Down Cur-
rent— TTL Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= 3.6V
70ns
I
OUT
= 0 mA
55ns
CMOS Levels
Max. V
CC
, CE
1
≥V
IH
,
70ns
CE
2
<V
IH
55ns
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE
1
≥
V
CC
– 0.3V,CE
2
<0.3
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V, f = 0
f = f
MAX
= 1/t
RC
I
OH
= –1.0 mA
I
OL
= 2.1 mA
Test Conditions
V
CC
= 2.7V
V
CC
= 2.7V
2
–0.5
–1
–1
20
23
15
17
Min.
2.4
0.4
V
CC
+
0.5V
0.8
+1
+1
40
50
300
350
µA
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB2
Automatic CE
Power-Down Cur-
rent— CMOS Inputs
0.4
30
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,V
CC
= Vcc
(typ)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
[3]
(Junction to Ambient)
Thermal Resistance
[3]
(Junction to Case)
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer print-
ed circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Unit
°C/W
°C/W
3
WCMA1008U1X
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
Typ
10%
GND
Rise Time: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall time: 1 V/ns
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
R
TH
V
TH
Parameters
R1
R2
R
TH
V
TH
3.3V
1213
1378
645
1.75
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
t
CDR[3]
t
R[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
V
CC
= 2V, CE
1
≥
V
CC
– 0.3V,
CE
2
< 0.3V
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
0
t
RC
Conditions
Min.
1.6
0.4
20
Typ.
[2]
Max.
Unit
V
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
1.8V
t
CDR
V
DR
> 1.6V
1.8V
t
R
CE
Note:
4. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µ
s or stable at V
CC(min.)
>
100
µ
s.
4
WCMA1008U1X
Switching Characteristics
Over the Operating Range
[5]
WCMA1008U1X-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
[8,]
WCMA1008U1X-70
Min.
70
Max.
Unit
ns
70
10
70
35
10
25
10
25
0
70
70
60
60
0
0
55
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
ns
ns
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Low Z
[6]
CE
1
HIGH or CE
2
LOW to High Z
[6, 7]
CE
1
LOW and CE
2
HIGH to Power-Up
CE
1
HIGH or CE
2
LOW to Power-Down
Write Cycle Time
CE
1
LOW and CE
2
HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
Min.
55
Max.
55
5
55
20
10
20
10
20
0
55
55
45
45
0
0
45
25
0
20
5
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
8. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
and CE
2
= V
IH
. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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