SY89297U
2.5V, 3.2Gbps Precision CML Dual-Channel
Programmable Delay
General Description
The SY89297U is a DC-3.2Gbps programmable, two-
channel delay line. Each channel has a delay range from
2ns to 7ns (5ns delta delay) in programmable increments
as small as 5ps. The delay step is extremely linear and
monotonic over the entire programming range, with 20ps
INL over temperature and voltage.
The delay varies in discrete steps based on a serial control
word provided by the 3-pin serial control (SDATA, SCLK,
and SLOAD). The control word for each channel is 10-bits.
Both channels are programmed through a common serial
interface. For increased delay, multiple SY89297U delay
lines can be cascaded together.
The SY89297U provides two independent 3.2Gbps delay
lines in an ultra-small 4mm x 4mm, 24-pin MLF
®
package.
For other delay line solutions, consider the SY89295U and
SY89296U single-channel delay lines. Evaluation boards
are available for all these parts.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Precision Edge
®
Features
•
Dual-channel, programmable delay line
•
Serial programming interface (SDATA, SCLK, SLOAD)
•
Guaranteed AC performance over temperature and
voltage:
– > 3.2Gbps/1.6GHz f
MAX
•
Programming Accuracy:
– Linearity: -15ps to +15ps INL
– Monotonic: -10ps to +20ps
– Resolution: 5ps programming increments
•
Low-jitter design: 2ps
RMS
typical random jitter
•
•
•
•
•
Programmable delay range: 5ns delay range
Cascade capability for increased delay
Low voltage operation: 2.5V ± 5%
Temperature range: 0°C to +75°C
Available in 24-pin (4mm x 4mm) MLF
®
(QFN)
Applications
•
•
•
•
Clock de-skewing
Timing adjustments
Aperture centering
System calibration
Markets
•
•
•
•
Automated test equipment
Digital radio and video broadcasting
Closed caption encoders/decoders
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame
and MLF are registered trademarks of Amkor, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2008
M9999-081208-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89297U
Ordering Information
(1)
Part Number
SY89297UMH
SY89297UMHTR
(2)
Package
Type
MLF-24
MLF-24
Operating
Range
Commercial
Commercial
Package Marking
297U with
Pb-Free bar line indicator
297U with
Pb-Free bar-line indicator
Lead Finish
Pb-Free
NiPdAu
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
Pin Configuration
24-Pin MLF
®
(MLF-24)
Truth Tables
Inputs
INA, INB
0
1
/INA, /INB
1
0
QA, QB
0
1
Outputs
/QA, /QB
1
0
Table 1. Inputs/Outputs
Input Enable (Latches Outputs)
/ENA, /ENB
1
0
Q, /Q (A, B)
Q = Low
/Q = HIGH
IN, /IN Delayed
(normal operation)
Table 2. Input Enable (Latches Outputs)
August 2008
2
M9999-081208-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89297U
Functional Block Diagram
August 2008
3
M9999-081208-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89297U
Pin Description
Pin Number
1
2
3
Pin Name
INA
/INA
VTA
Pin Function
Channel A differential Input: INA and /INA pins receive the Channel A data. QA and /QA are
the delayed product of INA and /INA. Each input is internally terminated to VTA through a
50Ω resistor (100Ω across INA and /INA).
Input A Termination Center-Tap: Each side of the differential input pair terminates to this pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” section.
Input B Termination Center-Tap: Each side of the differential input pair terminates to this pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” section.
Channel B differential Input: INB and /INB pins receive the Channel B data. QB and /QB are
the delayed product of INB and /INB. Each input is internally terminated to VTB through a
50Ω resistor (100Ω across INB and /INB).
Reference Voltage Output: For AC-coupled input signals, this pin can bias the inputs IN and
/IN. Connect VREF-AC directly to the VT input pin for each channel. De-couple to V
CC
using
a 0.01µF capacitor. Maximum sink/source current is ±0.5mA. For DC-coupled input
applications, leave VREF-AC pin floating.
Negative Supply: Exposed pad must be connected to a ground plane
that is the same potential as the ground pins.
CMOS/TTL-compatible Enable Input: When the /ENA pin is pulled HIGH, QA is held LOW and
/QA goes HIGH after the programmed delay propagates through the part. /ENA contains a
67k ohm pull-down resistor and defaults LOW when left floating. Logic threshold level is Vcc/2
CMOS/TTL-compatible Enable Input: When the /ENB pin is pulled HIGH, QB is held LOW and
/QB goes HIGH after the programmed delay propagates through the part. /ENB contains a
67k ohm pull-down resistor and defaults LOW when left floating. Logic threshold level is Vcc/2
Power Supply: 2.5V +5%. Bypass each supply pin with 0.1µF//0.01µF low ESR capacitors.
CML Differential Output: QB and /QB are the delayed product of INB, /INB. CML outputs are
terminated at the destination with 100Ω across the pair. See “CML Output Termination”
section.
CML Differential Output: QA and /QA are the delayed product of INA, /INA. CML outputs are
terminated at the destination with 100Ω across the pair. See “CML Output Termination”
section.
CMOS/TTL-compatible 3-pin serial programming control inputs: The 3-pin serial control sets
each channel’s IN to Q delay. DA(0:9) control channel A delay. DB(0:9) control channel B. To
program the two channels, insert a 20-bit word (DA0:DA9 and DB0:DB9) into SDATA and
clock in the control bits with SCLK. Maximum input frequency to SCLK is 40MHz. Data is
loaded into the serial registers on the L-H transition of SCLK. After all 20-bits are clocked in,
SLOAD latches the new delay bits. These pins have internal pull-downs at the inputs. See
“AC Electrical Characteristics” for delay values. Logic threshold level is Vcc/2. SCLK and
SDATA contain a 67k ohm pull-down resistor and default LOW when left floating.
CMOS/TTL-compatible 3-pin serial programming control input: SLOAD controls the latches
that transfer scanned data to the delay line. These latches are transparent when SLOAD is
high. Data transfers from the latch to the delay line on a L-H transition of SLOAD. SLOAD
has to transition H-L before new data is loaded in the scan chain. When SLOAD is high, the
latches are transparent and SCLK cannot switch. Otherwise, new data will immediately
transfer to the scan chain. Logic threshold level is Vcc/2. SLOAD contains a 67kΩ pull-down
resistor and defaults LOW when left floating.
CMOS/TTL-compatible output: This pin is used to support cascading multiple SY89297U
delay lines. Serial data is clocked into the SDATA input and is clocked out of SOUT into the
next SY89297U delay line. SOUT pin includes an internal 550Ω pull-up resistor.
4
5
6
VTB
INB
/INB
7
VREF-AC
GND,
Exposed Pad
/ENA
8, 11, 20
9
10
12, 15, 16, 19
13
14
17
18
/ENB
VCC
/QB
QB
/QA
QA
23
22
SCLK
SDATA
24
SLOAD
21
SOUT
August 2008
4
M9999-081208-B
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89297U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) ................................. –0.5V to +4.0V
Input Voltage (V
IN
) ......................................... –0.5V to V
CC
CML Output Voltage (V
OUT
)… .........V
CC
-1.0V to V
CC
+0.5V
Current (V
T
)
Source or sink current on VT pin ...................... ±70mA
Input Current
Source or sink current on (IN, /IN).................... ±35mA
Current (V
REF
)
Source or sink current on V
REF-AC(2)
................ .±0.5mA
Maximum operating Junction Temperature ............ 125°C
Lead Temperature (soldering, 20sec.)..................... 260°C
Storage Temperature (T
s
) ....................... –65°C to +150°C
Operating Ratings
(3)
Supply Voltage (V
CC
) ........................... +2.375V to +2.625V
Ambient Temperature (T
A
).............................. 0°C to +75°C
Package Thermal Resistance
(4)
MLF
®
(θ
JA
)
Still-Air ...............................................................43°C/W
MLF
®
(ψ
JB
)
Junction-to-Board ...........................................30.5°C/W
DC Electrical Characteristics
(5)
T
A
= 0°C to +75°C, Channels A and B, unless otherwise stated.
Symbol
V
CC
I
CC
R
IN
R
DIFF_IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF-AC
V
T_IN
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for
extended periods may affect device reliability.
2. Due to the limited drive capability, use for input of the same package only.
3. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
4. Thermal performance on MLF packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (GND).
5. The circuit is designed to meet the DC specifications shown in the table after thermal equilibrium has been established.
®
Parameter
Power Supply Voltage Range
Power Supply Current
Input Resistance
(IN-to-VT, /IN-to-VT)
Differential Input Resistance
(IN-to-/IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
(|IN - /IN|)
Output Reference Voltage
Voltage from Input to V
T
Condition
Max. V
CC
, Both Channels combined,
Output Load Included
Min
2.375
Typ
2.5
195
Max
2.625
250
55
110
V
CC
V
IH
–0.1
1.0
Units
V
mA
Ω
Ω
V
V
V
V
45
90
1.2
0
see Figure 5a
see Figure 5b
0.1
0.2
V
CC
–1.3
50
100
V
CC
–1.2
V
CC
–1.1
1.28
V
V
August 2008
5
M9999-081208-B
hbwhelp@micrel.com
or (408) 955-1690
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
