CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
72-Mbit DDR II SIO SRAM 2-Word
Burst Architecture
Features
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Functional Description
The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and
CY7C1524KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with DDR II SIO (Double Data Rate Separate I/O)
architecture. The DDR II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR
II SIO has separate data inputs and data outputs to completely
eliminate the need to “turnaround” the data bus required with
common I/O devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1522KV18, two 9-bit words in the case of
CY7C1529KV18, two 18-bit words in the case of
CY7C1523KV18, and two 36-bit words in the case of
CY7C1524KV18 that burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
333 MHz Clock for High Bandwidth
2-word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Synchronous Internally Self timed Writes
DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
1.8V Core Power Supply with HSTL Inputs and Outputs
Variable Drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V–V
DD
)
❐
Supports both 1.5V and 1.8V IO supply
Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
JTAG 1149.1 compatible Test Access Port
Phase Locked Loop (PLL) for accurate Data Placement
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Configurations
CY7C1522KV18 – 8M x 8
CY7C1529KV18 – 8M x 9
CY7C1523KV18 – 4M x 18
CY7C1524KV18 – 2M x 36
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
333 MHz
333
510
510
520
640
300 MHz
300
480
480
490
600
250 MHz
250
420
420
430
530
200 MHz
200
370
370
380
450
167 MHz
167
340
340
340
400
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-00438 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 29, 2010
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Logic Block Diagram (CY7C1522KV18)
D
[7:0]
8
Write Add. Decode
Read Add. Decode
A
(21:0)
22
Address
Register
Write
Data Reg
Write
Data Reg
4M x 8 Array
4M x 8 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
NWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
16
8
8
Reg.
Reg.
Reg. 8
8
8
CQ
Q
[7:0]
Logic Block Diagram (CY7C1529KV18)
D
[8:0]
9
Write Add. Decode
Read Add. Decode
A
(21:0)
22
Address
Register
Write
Data Reg
Write
Data Reg
4M x 9 Array
4M x 9 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[0]
Control
Logic
CLK
Gen.
Read Data Reg.
18
9
9
Reg.
Reg.
Reg. 9
9
9
CQ
Q
[8:0]
Document Number: 001-00438 Rev. *F
Page 2 of 32
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Logic Block Diagram (CY7C1523KV18)
D
[17:0]
18
Write Add. Decode
Read Add. Decode
A
(20:0)
21
Address
Register
Write
Data Reg
Write
Data Reg
2M x 18 Array
2M x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
36
18
18
Reg.
Reg.
Reg. 18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1524KV18)
D
[35:0]
36
Write Add. Decode
Read Add. Decode
A
(19:0)
20
Address
Register
Write
Data Reg
Write
Data Reg
1M x 18 Array
1M x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[3:0]
Control
Logic
CLK
Gen.
Read Data Reg.
72
36
36
Reg.
Reg.
Reg. 36
36
CQ
36
Q
[35:0]
Document Number: 001-00438 Rev. *F
Page 3 of 32
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Contents
Features ............................................................................ 1
Configurations .................................................................. 1
Functional Description..................................................... 1
Logic Block Diagram (CY7C1522KV18).......................... 2
Logic Block Diagram (CY7C1529KV18).......................... 2
Logic Block Diagram (CY7C1523KV18).......................... 3
Logic Block Diagram (CY7C1524KV18).......................... 3
Contents ............................................................................ 4
Pin Configuration .............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
DDR Operation............................................................ 9
Depth Expansion ......................................................... 9
Programmable Impedance .......................................... 9
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ...................................................... 13
Test Data-Out (TDO)................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ...........................................................
TAP Instruction Set ...................................................
TAP Controller State Diagram.......................................
TAP Controller Block Diagram......................................
TAP Electrical Characteristics ......................................
TAP AC Switching Characteristics ...............................
TAP Timing and Test Conditions ..................................
Identification Register Definitions ................................
Scan Register Sizes .......................................................
Instruction Codes...........................................................
Boundary Scan Order ....................................................
Power Up Sequence in DDR II SRAM ...........................
Power Up Sequence .................................................
PLL Constraints.........................................................
Maximum Ratings...........................................................
Operating Range ............................................................
Electrical Characteristics ..............................................
DC Electrical Characteristics.....................................
AC Electrical Characteristics.....................................
Capacitance ....................................................................
Thermal Resistance .......................................................
Switching Characteristics .............................................
Switching Waveforms ....................................................
Ordering Information .....................................................
Package Diagram ...........................................................
Document History Page.................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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Document Number: 001-00438 Rev. *F
Page 4 of 32
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CY7C1522KV18, CY7C1529KV18
CY7C1523KV18, CY7C1524KV18
Pin Configuration
The pin configurations for CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1522KV18 (8M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
A
NC
NC
NC
Q4
NC
Q5
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
CY7C1529KV18 (8M x 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
NC
NC
D5
NC
NC
D6
V
REF
NC
NC
Q7
NC
D8
NC
TCK
3
A
NC
NC
NC
Q5
NC
Q6
V
DDQ
NC
NC
D7
NC
NC
Q8
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
V
REF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-00438 Rev. *F
Page 5 of 32
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