DS1MX7 Device
DS1 Mapper 7-Channel
TXC-04201B
DATA SHEET
FEATURES
• Seven independent 1.544 Mbit/s DS1 mappers
• Single byte-parallel Telecom Bus @ 6.48 MHz (28
Slots) or 19.44 MHz (84 Slots)
• Floating VT1.5 byte-synchronous mapping with
signaling only for use with or without a slip buffer
• Asynchronous mapping for DS1
• SONET mapping (VT1.5) or SDH mapping
(TU-11 in AU-3 or TU-11 in TUG-3)
• AMI, B8ZS or NRZ codec for DS1s
• Serial I/O for control of DS1 line interface
transceivers or framers
• Telecom Bus and DS1 loopbacks with integral
PRBS generator and analyzer
• VT1.5/TU-11 pointer tracking and generation
• VT1.5/TU-11 overhead processing and insertion
• one-second latched performance registers and
counters
• DS1 alarm detection and generation
• Auxiliary port for J2, V5, Z6/N2, Z7/K4 and O-bit
access
• Ring port for USHR/P support
• Gapped clock option for Internet Applications
without need for a framer
• Intel / Motorola-compatible microprocessor
interface
• 3-bit RDI support
• Boundary Scan capability (IEEE 1149.1)
• Single +5 V,
±5
% power supply
• 208-pin plastic quad flat package
Line Transceiver Common
Control Interface
+5V
4
DESCRIPTION
The DS1MX7 is a seven-channel byte-synchronous and
asynchronous DS1 mapper. Both SONET and SDH map-
pings are provided per Bellcore GR-253-CORE (VT1.5)
and ITU-T G.707 3-96 (TU-11). A single add/drop Tele-
com Bus is provided that can operate at either 6.48 or
19.44 MHz, which is compatible with other TranSwitch
devices. VT1.5/TU-11 pointer tracking and overhead
extraction/processing with full error and alarm control is
provided. VT1.5/TU-11 pointer calculation and overhead
assembly is also provided. Alarm and error mappings
from drop to add and SONET/SDH to/from DS1 are pro-
vided. Jitter performance is achieved with a fully digital
threshold modulator and DPLL that meets GR-253-CORE
MTIE requirements without external de-jitter buffers. For
the DS1 line, AMI, B8ZS and NRZ line codes are sup-
ported with full alarm detection and generation per ANSI
T1.231-1997 draft. Each channel is independently pro-
grammable for mixed service applications. Access to sta-
tus and control bits is provided via an Intel/Motorola-
compatible microprocessor interface. Diagnostic, test,
and maintenance functions are provided, including
boundary scan, PRBS generator/analyzer and loopbacks.
APPLICATIONS
• SONET/SDH terminal or add/drop multiplexers sup-
porting both asynchronous and byte-synchronous
modes
• Unidirectional or bidirectional ring applications
• SONET Remote Digital Terminal Equipment
• SONET CPE Equipment requiring access to DS0s
• SONET/SDH Test Equipment
• Internet Access Equipment
LINE SIDE
DS1 Dual Rail /
NRZ Data &
Clocks (x 7)
Ring Port
3
6
18
SYSTEM SIDE
Add Bus
4
Line Transceiver
Serial Interface (x 7)
DS1MX7
DS1 Mapper
7-Channel
TXC-04201B
3
Microprocessor
Interface
5
Telecom Bus
Interface (x 1)
Drop Bus
13
10
2
U.S. Patents No. 4,967,405; 5,033,064;
5,040,170; 5,265,096; 5,289,507; 5,297,180; 5,528,598; 5,535,218
U.S. and/or foreign patents issued or pending
Copyright
2001 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
System
Test Access Auxiliary Port
Clocks Port Interface for
Boundary Scan
Document Number:
TXC-04201B-MB
Ed. 4, September 2001
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, Connecticut 06484
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
•
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DS1MX7
TXC-04201B
DATA SHEET
TABLE OF CONTENTS
Section
Page
List of Figures ....................................................................................................................................3
Feature List........................................................................................................................................ 4
Features that are Independently Selectable for each of the Mappers........................................ 4
Features that are only Selectable for the Seven Mappers as a Group....................................... 7
Block Diagram ................................................................................................................................... 9
Block Diagram Description .............................................................................................................. 10
Pin Diagram ..................................................................................................................................... 15
Pin Descriptions............................................................................................................................... 16
Absolute Maximum Ratings and Environmental Limitations............................................................ 25
Thermal Characteristics................................................................................................................... 25
Power Requirements ....................................................................................................................... 25
Input, Output and Input/Output Parameters..................................................................................... 26
Timing Characteristics ..................................................................................................................... 29
Operation ......................................................................................................................................... 46
General Mapper Application Overview ..................................................................................... 46
Line Interface Selection ............................................................................................................ 46
Asynchronous Operation with the Line Interface............................................................... 47
Byte-synchronous Operation with the Line Interface......................................................... 49
Receive Data and Signaling Highway Operation .............................................................. 49
Transmit Data and Signaling Highway Operation ............................................................. 52
The Synchronizer, Mapper and Overhead Generator ....................................................... 54
Pointer Generation and Telecom Bus Slot Selection ........................................................ 57
VT/TU Pointer Tracking and Telecom Bus Slot Selection................................................. 60
The Demapper .................................................................................................................. 63
Desynchronization and Pointer Leak Rate Calculations ................................................... 65
Jitter Measurements ................................................................................................................. 68
Microprocessor Interface and Common Control/Status I/O...................................................... 74
Serial Port Control Interface ..................................................................................................... 77
DS1MX7 Channel Testing using the PRBS Generator and Analyzer ............................... 78
Telecom Bus Interface.............................................................................................................. 79
Multiplex Format and Mapping Information .............................................................................. 83
Auxiliary Port ............................................................................................................................ 89
Ring Port................................................................................................................................... 91
Test Access Port ...................................................................................................................... 91
Boundary Scan Support .................................................................................................... 92
Device Reset Procedure........................................................................................................... 99
Memory Map.................................................................................................................................. 100
Memory Map Descriptions ............................................................................................................. 104
Common Memory Map ........................................................................................................... 104
Per Channel Control Registers............................................................................................... 120
Per Channel Status Registers ................................................................................................ 131
Application Diagrams..................................................................................................................... 144
Package Information...................................................................................................................... 146
Ordering Information...................................................................................................................... 147
Related Products ........................................................................................................................... 147
Standards Documentation Sources ............................................................................................... 148
List of Data Sheet Changes........................................................................................................... 150
Documentation Update Registration Form*
.............................................................................. 153
* Please note that TranSwitch provides documentation for all of its products. Current editions of many
documents are available from the Products page of the TranSwitch Web site at www.transwitch.com.
Customers who are using a TranSwitch Product, or planning to do so, should register with the
TranSwitch Marketing Department to receive relevant updated and supplemental documentation as
it is issued. They should also contact the Applications Engineering Department to ensure that they
are provided with the latest available information about the product, especially before undertaking
development of new designs incorporating the product.
TXC-04201B-MB
Ed. 4, September 2001
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
LIST OF FIGURES
Figure
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DS1MX7
TXC-04201B
Page
DS1MX7 TXC-04201B Block Diagram................................................................................ 9
VT1.5/ TU-11 Asynchronous and Byte-synchronous Mappings........................................ 12
DS1MX7 TXC-04201B Pin Diagram ................................................................................. 15
Tributary Input Timing ....................................................................................................... 29
Tributary Output Timing..................................................................................................... 30
Signaling Highway Structure ............................................................................................ 31
Serial Control Port Structure and Timing .......................................................................... 32
Telecom Bus Input Timing - 6.48 MHz Operation ............................................................. 33
Telecom Bus Input Timing - 19.44 MHz Operation ........................................................... 34
Telecom Bus Output Timing - 6.48 MHz Operation .......................................................... 35
Telecom Bus Output Timing - 19.44 MHz Operation ........................................................ 36
Auxiliary Port Timing ......................................................................................................... 37
Ring Port Timing................................................................................................................ 38
Datacom Mode Output Timing .......................................................................................... 39
Datacom Mode Input Timing ............................................................................................. 40
Intel Microprocessor Read Cycle Timing........................................................................... 41
Motorola Microprocessor Read Cycle Timing ................................................................... 42
Intel Microprocessor Write Cycle Timing .......................................................................... 43
Motorola Microprocessor Write Cycle Timing.................................................................... 44
Boundary Scan Timing ...................................................................................................... 45
Line Interface for Dual Unipolar Mode............................................................................... 48
Line Interface for NRZ Mode ............................................................................................. 48
Byte-synchronous Interface to a DS1 Framer ................................................................... 49
System Interface Receive Framing Format....................................................................... 51
System Interface Receive Signaling Format ..................................................................... 51
System Interface Transmit Framing Format...................................................................... 53
System Interface Transmit Signaling Format .................................................................... 53
VT/TU Pointer Tracking State Machine............................................................................. 62
Pointer Leak Rate Algorithm ............................................................................................. 67
Jitter Tolerance Test Setup ............................................................................................... 68
Jitter Tolerance Measurements......................................................................................... 69
Jitter Transfer Test Setup.................................................................................................. 70
Jitter Transfer Measurements ........................................................................................... 70
Jitter Generation Test Setup ............................................................................................. 71
Standard Pointer Test Sequences .................................................................................... 73
Shadow Register Operation .............................................................................................. 77
Serial Interface Operation ................................................................................................. 78
Loopbacks and Built-in PRBS Testing of the DS1MX7 ..................................................... 79
Telecom Bus Structure; SONET or VC-3 SDH; Telecom Bus @ 6.48 MHz ..................... 81
Telecom Bus Structure; TUG-3 SDH; Telecom Bus @ 19.44 MHz .................................. 82
STS-1 SPE Mapping ......................................................................................................... 83
STS-3/AU-3 Mapping ........................................................................................................ 85
STM-1/VC-4 Mapping........................................................................................................ 87
Auxiliary Port Operation .................................................................................................... 89
Auxiliary Port Address Designation ................................................................................... 90
Ring Port Operation........................................................................................................... 91
Boundary Scan Schematic ................................................................................................ 93
DS1MX7 TXC-04201B Applications................................................................................ 144
Some DS1MX7 TXC-04201B Byte-synchronous Applications........................................ 145
DS1MX7 TXC-04201B 208-Pin Plastic Quad Flat Package ........................................... 146
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TXC-04201B-MB
Ed. 4, September 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DS1MX7
TXC-04201B
FEATURE LIST
DATA SHEET
The DS1MX7 device is a highly-featured seven-channel DS1 (T1) mapper for use in a wide variety of interface,
transmission and switching applications. Seven independent DS1 asynchronous / byte-synchronous mappers
are provided in a single monolithic VLSI device using sub-micron CMOS technology. Powered from a single
+5.0 volt supply, the device dissipates less than one watt typically. The DS1MX7 is provided in a 208-pin plastic
quad flat package. Its ambient operating temperature range extends from -40 ×C to 85 ×C with 0 ft/min airflow.
The DS1MX7 device has been designed to meet the latest industry standards, namely:
• ANSI T1.102- 1993
• ANSI T1.105- 1991
• ANSI T1.107- 1995
• ANSI T1.231 (1993 and 1997 draft)
• ANSI T1.403-1995
• AT&T Pub. 62411 (December 1990)
• Bellcore GR-253-CORE (Issue 2)
• Bellcore TR-NWT-000496 (Issue 3)
• Bellcore GR-499-CORE (Issue 1)
• IEEE 1149.1- 1990, -1994
• ITU-T G.707 3-96
• ITU-T G.783
FEATURES THAT ARE INDEPENDENTLY SELECTABLE FOR EACH OF THE MAPPERS
Line Interface Options
• Meets ANSI and Bellcore input jitter requirements
• Rail (for asynchronous mapping only)
B8ZS or AMI
ANSI compliant LOS detector
ANSI compliant AIS detector
12-Bit BPV counters with excessive zeros option
• NRZ option (for asynchronous and byte-synchronous mapping)
Clock polarity selection for clock in/out
NRZ data inversion and clock edge options (separate transmit and receive control)
For asynchronous use, negative rail can be used to count externally detected code
violations
• Programmable clock edges for transmit and receive data
• External pin per channel for status (may be programmed to combine with internal AIS and
LOS to support external LOC detector)
• Clock slave for asynchronous input; clock and multiframe synchronization (3 ms), master or
slave, for byte-synchronous input
• Separate signaling highway for byte-synchronous, carries ABCD signaling bits and AIS /
Yellow alarm information in and out of the DS1MX7
• External pin-controlled shut down of all DS1 line drive pins for card protection
• Gapped clock option in place of signaling for 1536 kHz datacom in byte-synchronous
operation
• CRC-6 generation (DS1 input) and error counting (DS1 output) in byte-synchronous mapping
TXC-04201B-MB
Ed. 4, September 2001
- 4 of 154 -
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
Mapping And Synchronizer Features
• Mapping to SONET or SDH columns according to GR-253-CORE or ITU G.709
DS1MX7
TXC-04201B
• Per channel selectable asynchronous and byte-synchronous mapping to a floating
VT1.5 or TU-11 for both mapping and demapping
• Overhead assembly with BIP-2 calculation, REI-FEBE (microprocessor or received BIP-2
error), signal label (microprocessor value), RDI (microprocessor value or via received signal
label mismatch, VT AIS, VT LOP, or unequipped) and RFI (microprocessor value or DS1
Yellow from signaling highway)
• Pointer calculation (fixed at 78 for asynchronous, calculated for byte-synchronous mode) with
generated pointer increment and decrement counters (4 bits each)
• In byte-synchronous mode, line clock may be an input (’modified byte-synchronous’) or an
output (’true byte-synchronous’)
• Multiplexing of signaling bits from the signaling highway with P
0
/P
1
bit generation
• Unequipped and Unassigned VT payload generation
• VT AIS generation (microprocessor value, AIS from signaling highway, loss of frame on byte-
synchronous, or AIS / LOS / external pin from line decoder)
• Threshold modulator to reduce demapping jitter and wander
• Tracking of input multiframe pulses by pointer movements in byte-synchronous mode
Demapping And Desynchronizer Features
• Asynchronous or byte-synchronous per channel, programmable to match mapper mode
• Digital PLL with 2 Hz low pass filter to track up to + 250 Hz nominal DS1 signal providing a
smooth clock output with no need for an external de-jitter buffer
• Separate +5 byte pointer leak buffer with programmable dual slope leak rate
(8 ms to 2048 ms per bit in 8 ms steps, automatically doubled to 16 ms to 4096 ms per bit in
16 ms steps within +12 bits of center of pointer leak buffer)
• Power down with all-zeros or all-ones sent to line interface
• Demapping of SONET or SDH columns according to GR-253-CORE or ITU G.709
• Asynchronous and byte-synchronous demapping of a floating VT1.5 / TU-11
• Pointer tracking and extraction of overhead (V5 and Z7/K4), LOP AIS, SS and NDF with
,
received pointer increment and decrement counters (4 bits each)
• Overhead processing with BIP-2 calculation and error counting (12-bit, with overflow), REI
(FEBE) counting (12-bit, with overflow), RDI (1- and 3-bit)/ RFI / signal label de-bouncing and
detection, signal label mismatch / unequipped detection
• De-multiplexing of signaling bits to the signaling highway with multiframe generation for byte-
synchronous
• DS1 AIS from microprocessor value, VT AIS, VT LOP signal label mismatch or unequipped
,
• DS1 Yellow to signaling highway from RFI
Fractional T1 For Frame Relay, ATM AAL1 Access
• Framer not required for many applications
• Receive and transmit gapped clock (1536 kbit/s) per mapper in byte-synchronous mode
• CRC-6 generation and checking
• Direct connection to multichannel HDLC or ATM devices for N x 56 or N x 64 kbit/s service
• Internal DPLL to minimize received jitter
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TXC-04201B-MB
Ed. 4, September 2001
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