Preliminary
HY5V66D(L)F(P) Series
4Banks x 1M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V66D(L)F(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5V66DF6 is organized as 4banks of 1,048,576x16.
HY5V66D(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
•
Voltage : VDD, VDDQ 3.3V supply voltage
All device pins are compatible with LVTTL interface
54Ball FBGA
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM, LDQM
•
Internal four banks operation
•
Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
•
•
•
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY5V66DF-K
HY5V66DF-H
HY5V66DF-P
HY5V66DF-S
HY5V66DFP-K
HY5V66DFP-H
HY5V66DFP-P
HY5V66DFP-S
HY5V66DLF-K
HY5V66DLF-H
HY5V66DLF-P
HY5V66DLF-S
HY5V66DLFP-K
HY5V66DLFP-H
HY5V66DLFP-P
HY5V66DLFP-S
Clock
Frequency
133MHz
133MHz
100MHz
100MHz
133MHz
133MHz
100MHz
100MHz
133MHz
133MHz
100MHz
100MHz
133MHz
133MHz
100MHz
100MHz
CAS
Latency
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
Organization
Interface
Power
Package
54Ball FBGA, Lead
Nornal
54Ball FBGA, Lead
Free
4Banks x
1Mbits x16
LVTTL
54Ball FBGA, Lead
Low
Power
54Ball FBGA, Lead
Free
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / Feb. 2004
2
Preliminary
HY5V66D(L)F(P) Series
4Banks x 1M x 16bits Synchronous DRAM
BALL DESCRIPTION
Ball Out
F2
SYMBOL
CLK
TYPE
INPUT
DESCRIPTION
Clock : The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among (deep) power down, suspend or
self refresh
Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and
LDQM
Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
Data Mask : Controls output buffers in read mode and masks input data
in write mode
F3
CKE
INPUT
G9
G7,G8
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9,
G2
F8, F7, F9
F1, E8
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1, A2
A9, E7, J9, A1,
E3, J1
A7, B3, C7, D3,
A3, B7, C3, D7
E2, G1
CS
BA0, BA1
INPUT
INPUT
A0 ~ A11
INPUT
RAS, CAS, WE
UDQM, LDQM
INPUT
INPUT
DQ0 ~ DQ15
I/O
Data Input/Output : Multiplexed data input/output pin
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
SUPPLY
SUPPLY
-
Power supply for internal circuits
Power supply for output buffers
No connection
Rev. 0.1 / Feb. 2004
4
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
