8Mx64 bits
PC133 SDRAM SO DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V63M801 X-Series
DESCRIPTION
The Hyundai HYM71V63M801 X-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of
four 8Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP
package on a 144pin glass-epoxy printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each
SDRAM are mounted on the PCB.
The HYM71V63M801 X-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and
addition of 64Mbytes memory. The HYM71V63M801 X-Series are offering fully synchronous operation referenced to a
positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths
are internally pipelined to achieve very high bandwidth.
FEATURES
•
PC133/PC100MHz support
•
144pin SDRAM SO DIMM
•
Serial Presence Detect with EEPROM
•
1.00” (25.40mm) Height PCB with Double Sided
components
•
Single 3.3
±
0.3V power supply
•
All devices pins are compatible with LVTTL interface
•
Data mask function by DQM
•
SDRAM internal banks : four banks
•
Module bank : one physical bank
•
Auto refresh and self refresh
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
-. 1, 2, 4, 8 or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
•
Programmable /CAS Latency
-. 2, 3 Clocks
ORDERING INFORMATION
PART NO.
HYM71V63M801TX-75
HYM71V63M801LTX-75
MAX.
FREQUENCY
133MHz
133MHz
INTERNAL
BANK
4 Banks
REF.
4K
POWER
Normal
Low Power
SDRAM
PACKAGE
TSOP-II
PLATING
Gold
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.99
©1999
Hyundai MicroElectronics
PC133 SDRAM SO DIMM
HYM71V63M801 X-Series
PIN DESCRIPTION
PIN NAME
CK0, CK1
Clock Inputs
DESCRIPTION
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
Enables or disables all inputs except CK, CKE and DQM.
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
Row address : RA0~RA11, Column address : CA0~CA8
Auto-precharge flag : A10
/RAS define the operation.
Refer to the function truth table for details.
/CAS define the operation.
Refer to the function truth table for details.
/WE define the operation.
Refer to the function truth table for details.
Controls output buffers in read mode and masks input data in
write mode.
Multiplexed data input/output pins
Power supply for internal circuits and input/output buffers
Ground
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
No Connect or Don’ t Use
CKE0
/S0
BA0, BA1
Clock Enable
Chip Select
SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
DQM0~DQM7
DQ0~DQ63
VCC
VSS
SCL
SDA
NC
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
No Connect
Rev. 1.1/Dec.99
2
PC133 SDRAM SO DIMM
HYM71V63M801 X-Series
PIN ASSIGNMENTS
FRONT SIDE
PIN NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
NAME
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQ12
DQ13
DQ14
DQ15
VSS
NC
NC
PIN NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
BACK SIDE
NAME
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VCC
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VCC
DQ44
DQ45
DQ46
DQ47
VSS
NC
NC
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
CKE0
VCC
/CAS
NC
NC
135
137
139
141
143
FRONT SIDE
PIN NO.
NAME
NC
NC
VSS
NC
NC
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
DQ21
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10/AP
VCC
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VCC
PIN NO.
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK SIDE
NAME
NC
*CK1
VSS
NC
NC
VCC
DQ48
DQ49
DQ50
DQ51
VSS
DQ52
DQ53
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VCC
Voltage Key
61
63
65
67
69
CK0
VCC
/RAS
/WE
/S0
62
64
66
68
70
Note :
*. CK1 is connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.1/Dec.99
3
PC133 SDRAM SO DIMM
HYM71V63M801 X-Series
BLOCK DIAGRAM
Note :
1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitance of termination R/C for CK1 is 10pF.
Rev. 1.1/Dec.99
4
PC133 SDRAM SO DIMM
HYM71V63M801 X-Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36
–61
BYTE62
BYTE63
BYTE64
BYTE65
~71
BYTE72
FUNCTION
DESCRIBED
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random
Column Address
Burst Lengths Supported
# of Banks on Each SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
Module Bank Density
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
Data Signal Input Hold Time
Superset Information (may be used in future)
SPD Revision
Checksum for Bytes 0~62
Manufacturer JEDEC ID Code
....Manufacturer JEDEC ID Code
FUNCTION
-75
128 Bytes
256 Bytes
SDRAM
12
9
1 Banks
64 Bits
-
LVTTL
7.5ns
5.4ns
None
15.625µs
/ Self Refresh Supported
x16
None
tCCD = 1 CLK
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
10ns
6ns
-
-
20ns
15ns
20ns
45ns
64MB
1.5ns
0.8ns
1.5ns
0.8ns
-
Intel SPD 1.2
-
Hyundai JEDEC ID
Unused
HEI (Korea)
HEA (United States)
HEU (Europe)
VALUE
-75
80h
08h
04h
0Ch
09h
01h
40h
00h
01h
75h
54h
00h
80h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
0Fh
14h
2Dh
10h
15h
08h
15h
08h
00h
12h
A6h
ADh
FFh
01h
02h
03h
3, 8
2
1
NOTE
Manufacturing Location
Rev. 1.1/Dec.99
5
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