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HYMD525G726ALS4-L: 产品描述DDR DRAM Module, 256MX72, 0.75ns, CMOS, DIMM-184; 产品类别存储存储; 文件大小255KB，共16页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HYMD525G726ALS4-L概述

DDR DRAM Module, 256MX72, 0.75ns, CMOS, DIMM-184

HYMD525G726ALS4-L规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	DIMM, DIMM184
针数	184
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	DUAL BANK PAGE BURST
最长访问时间	0.75 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	125 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N184
内存密度	19327352832 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	72
功能数量	1
端口数量	1
端子数量	184
字数	268435456 words
字数代码	256000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	256MX72
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM184
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.18 A
最大压摆率	6.84 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
Base Number Matches	1

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256Mx72 bits

Registered DDR SDRAM DIMM

HYMD525G726A(L)S4-M/K/H/L

DESCRIPTION

Preliminary

Hynix HYMD525G726A(L)S4-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as 256Mx72 high-speed memory arrays. Hynix YMD525G726A(L)S4-

M/K/H/L series consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-

epoxy substrate. Hynix HYMD525G726A(L)S4-M/K/H/L series provide a high performance 8-byte interface in 5.25"

width form factor of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD525G726A(L)S4-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs

are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-

ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD525G726A(L)S4-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-

tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to

identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

2GB (256M x 72) Registered DDR DIMM based on

stacked 128Mx4 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

Error Check Correction (ECC) Capability

Registered inputs with one-clock delay

Phase-lock loop (PLL) clock driver to reduce loading

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

•

Fully differential clock operations (CK & /CK) with

125MHz/133MHz

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

ORDERING INFORMATION

Part No.

HYMD525G726A(L)S4-M

HYMD525G726A(L)S4-K

HYMD525G726A(L)S4-H

HYMD525G726A(L)S4-L

=2.5V

DDQ

=2.5V

Power Supply

Clock Frequency

133MHz (*DDR266 2-2-2)

133MHz (*DDR266A)

133MHz (*DDR266B)

125MHz (*DDR200)

Interface

Form Factor

SSTL_2

184pin Registered DIMM

5.25 x 1.7 x 0.15 inch

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.1/Jan. 2003

HYMD525G726ALS4-L相似产品对比

	HYMD525G726ALS4-L	HYMD525G726ALS4-H
描述	DDR DRAM Module, 256MX72, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 256MX72, 0.75ns, CMOS, DIMM-184
是否Rohs认证	不符合	不符合
零件包装代码	DIMM	DIMM
包装说明	DIMM, DIMM184	DIMM, DIMM184
针数	184	184
Reach Compliance Code	compliant	compliant
ECCN代码	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	0.75 ns	0.75 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	125 MHz	133 MHz
I/O 类型	COMMON	COMMON
JESD-30 代码	R-XDMA-N184	R-XDMA-N184
内存密度	19327352832 bit	19327352832 bit
内存集成电路类型	DDR DRAM MODULE	DDR DRAM MODULE
内存宽度	72	72
功能数量	1	1
端口数量	1	1
端子数量	184	184
字数	268435456 words	268435456 words
字数代码	256000000	256000000
工作模式	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C
组织	256MX72	256MX72
输出特性	3-STATE	3-STATE
封装主体材料	UNSPECIFIED	UNSPECIFIED
封装代码	DIMM	DIMM
封装等效代码	DIMM184	DIMM184
封装形状	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED
电源	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified
刷新周期	8192	8192
自我刷新	YES	YES
最大待机电流	0.18 A	0.18 A
最大压摆率	6.84 mA	6.84 mA
最大供电电压 (Vsup)	2.7 V	2.7 V
最小供电电压 (Vsup)	2.3 V	2.3 V
标称供电电压 (Vsup)	2.5 V	2.5 V
表面贴装	NO	NO
技术	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD
端子节距	1.27 mm	1.27 mm
端子位置	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED
Base Number Matches	1	1

HYMD525G726ALS4-L

HYMD525G726ALS4-L概述

HYMD525G726ALS4-L规格参数

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