Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
6350f
2
LT6350
ELECTRICAL CHARACTERISTICS
The
l
denotes specifications that apply over the full specified temperature range,
+
–
+
otherwise specifications are at T
A
= 25°C. Unless noted otherwise, V = 5V, V = 0V, V
+IN1
= V2 = Mid-Supply, V
SHDN
= V , R
L
= OPEN, R
F
=
SHORT, R
G
= OPEN. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
OUT1
+ V
OUT2
)/2. V
OUTDIFF
is defined as (V
OUT1
– V
OUT2
). See Figure 1.
PARAMETER
Differential Input-Referred Offset Voltage
CONDITIONS
V
S
= 5V
V
+IN1
= V2 = Mid-Rail
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
S
= 3V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
S
= 10V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
OS1
Input Offset Voltage, Op Amp 1
V
S
= 5V
V
+IN1
= V
–
+1.5V to V
+
V
+IN1
= V
–
to V
+
V
S
= 3V
V
+IN1
= V
–
+1.5V to V
+
V
+IN1
= V
–
to V
+
V
S
= 10V
V
+IN1
= V
–
+1.5V to V
+
V
+IN1
= V
–
to V
+
V
OS2
ΔV
OSDIFF
/ΔT
I
B1
Input Offset Voltage, Op Amp 2 (Note 6)
Differential Offset Voltage Drift
Input Bias Current, Op Amp 1
(at +IN1, –IN1)
Input Offset Current, Op Amp 1
(at +IN1, –IN1)
Input Bias Current, Op Amp 2 (at +IN2)
Input Offest Current, Op Amp 2
Input Voltage Noise Density, Op Amp 1
Input Current Noise Density, Op Amp 1
Input Voltage Noise Density, Op Amp 2
Input Current Noise Density, Op Amp 2
Differential Output Noise Voltage Density
Input Noise Voltage
SNR
V
+IN1
V
+IN2
R
IN
Output Signal to Noise Ratio
Input Voltage Range, +IN1
Input Voltage Range, +IN2
Input Resistance
Total Output Noise Including Both Op Amps
and On-Chip Resistors. Input Shorted. f = 10kHz
0.1Hz to 10Hz
V
OUTDIFF
= 8V
P-P
, 1MHz Noise Bandwidth
Guaranteed by CMRR1
Guaranteed by CMRR2
Single-Ended Input at +IN1
l
l
SYMBOL
V
OSDIFF
MIN
–0.4
–0.45
–0.77
–0.45
–0.8
–0.52
–0.78
–0.35
–1.5
–0.35
–1.5
–0.68
–1.5
–1.0
TYP
MAX
0.4
0.45
1.36
0.45
1.36
0.52
1.48
0.68
1.5
0.68
1.5
0.68
1.5
0.66
UNITS
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
μV/°C
μV/°C
μA
μA
μA
μA
μA
μA
μA
μA
nV/√Hz
pA/√Hz
nV/√Hz
pA/√Hz
nV/√Hz
nV
P-P
dB
l
±0.1
l
±0.1
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
±0.1
±0.08
±0.28
±0.08
±0.32
±0.07
±0.28
±0.1
5
5.5
V
S
= 3V, 5V, 10V
V
+IN1
= V2 = V
–
+1.5V to V
+
– 0.1V
V
+IN1
= V2 = V
–
+1.5V
V
+IN1
= V2 = V
+
–0.1V
V
+IN1
= Mid-Supply
V
+IN1
= V
–
V
+IN1
= V
+
V
+IN1
= Mid-Supply
V
+IN1
= V
–
V
+IN1
= V
+
V
+IN1
= V2 = Mid-Supply
V2 = Mid-Supply
Op Amp Input Referred
Op Amp Input Referred
–6.8
–8.0
–1
–1
–1
–1.2
–3.0
1.4
±0.1
±0.1
±0.1
2.5
±0.1
1.9
1.1
2.1
1
8.2
300
110
2.6
1
1
1
4.4
I
OS1
I
+IN2
I
OS2
e
n1
i
n1
e
n2
i
n2
e
n(OUT)
V
–
V
–
+1.5V
4
V
+
V
+
–0.1V
V
V
MΩ
6350f
3
LT6350
ELECTRICAL CHARACTERISTICS
The
l
denotes specifications that apply over the full specified temperature range,
+
–
+
otherwise specifications are at T
A
= 25°C. Unless noted otherwise, V = 5V, V = 0V, V
+IN1
= V2 = Mid-Supply, V
SHDN
= V , R
L
= OPEN, R
F
=
SHORT, R
G
= OPEN. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
OUT1
+ V
OUT2
)/2. V
OUTDIFF
is defined as (V
OUT1
– V
OUT2
). See Figure 1.
PARAMETER
Input Capacitance
CONDITIONS
Single-Ended Input at +IN1
l
l
l
l
l
l
l
l
l
l
l
l
SYMBOL
C
IN
CMRR1
MIN
82
77
72
67
93
85
96
80
2.7
50
TYP
1.8
94
94
88
82
118
110
118
108
MAX
UNITS
pF
dB
dB
dB
dB
dB
dB
dB
dB
Common Mode Rejection Ratio, Op Amp 1 V
S
= 5V, V
+IN1
= V
–IN1
= V
–
+1.5V to V
+
V
S
= 5V, V
+IN1
= V
–IN1
= V
–
+1.5V to V
+
V
S
= 5V, V
+IN1
= V
–IN1
= V
–
to V
+
V
S
= 3V, V
+IN1
= V
–IN1
= V
–
to V
+
Common Mode Rejection Ratio, Op Amp 2 V
S
= 5V, V
+IN1
= V2 = V
–
+1.5V to V
+
–0.1V
V
S
= 3V, V
+IN1
= V2 = V
–
+1.5V to V
+
–0.1V
V
S
= 10V, V
+IN1
= V2 = V
–
+1.5V to V
+
–0.1V
Power Supply Rejection Ratio (ΔV
S
/
ΔV
OSDIFF
)
Supply Voltage (Note 7)
Output Balance (ΔV
OUTDIFF
/ΔV
OUTCM
) (Note V
OUTDIFF
= 2V
8)
Closed-Loop Gain (ΔV
OUTDIFF
/Δ(V
+IN1
–V2))
Closed-Loop Gain Error
DC Linearity (Note 9)
V
+
= 5V, V
–
= 0V
V
+
= 5V, V
–
= –2V
V+ = 5V, V– = –2V, 16-Bit, 8V
P-P
No load
Sourcing 12.5mA
No load
Sourcing 12.5mA
V
+IN1
= Mid-Rail ±200mV, V
–IN1
= Mid-Rail
V
S
= 5V
V
S
= 5V
V
S
= 3V
V
S
= 2.7V to 12V
V
S
= 2.7V to 12V
SHDN
= V
+
SHDN
= V
–
V
S
= 3V
V
S
= 5V
V
S
= 5V
V
S
= 10V
V
S
= 3V, V
SHDN
= V
IL
V
S
= 5V, V
SHDN
= V
IL
V
S
= 10V, V
SHDN
= V
IL
Op Amp 1 (Non-Inverting)
Op Amp 2 (Inverting)
V
OUTDIFF
= 100mV
P-P
V
OUTDIFF
= 100mV
P-P
Δ(V
+IN1
–V2) = 4V
V
S
= 2.7V to 12V
CMRR2
PSRR
V
S
BAL
GAIN
GAIN
ERR
INL
12
68
2
V
dB
V/V
–0.6
±0.08
3
230
125
±1
1000
0.6
%
ppm/°C
μV
μV
LSB
Ω
ΔGAIN
ERR
/ΔT Closed-Loop Gain Error Drift
R
INT
V
OH
V
OL
I
SC
Internal Resistors
Output Swing to V
+
, Either Output (Note
10)
Output Swing to V
–
, Either Output (Note
10)
Output Short Circuit Current
l
l
l
l
55
360
55
260
±27
±15
±15
V
–
+ 2.0
–1
–45
±45
±45
±40
170
750
170
460
μV
μV
mV
mV
mA
mA
mA
l
l
l
l
l
l
l
l
l
l
l
l
V
IL
V
IH
I
SHDN
I
S
SHDN
Input Logic Low
SHDN
Input Logic High
SHDN
Pin Current
Supply Current
V
–
+ 0.3
1
–20
4.5
4.8
5.4
43
60
70
85
115
8.1
5.8
8.3
10.4
220
240
260
V
V
μA
μA
mA
mA
mA
mA
μA
μA
μA
MHz
MHz
MHz
MHz
I
S(SHDN)
Supply Current in Shutdown
GBW
BW
Gain-Bandwidth Product
Frequency = 1MHz
Differential –3dB Small Signal Bandwidth
l
23
19
33
6350f
4
LT6350
ELECTRICAL CHARACTERISTICS
The
l
denotes specifications that apply over the full specified temperature range,
+
–
+
otherwise specifications are at T
A
= 25°C. Unless noted otherwise, V = 5V, V = 0V, V
+IN1
= V2 = Mid-Supply, V
SHDN
= V , R
L
= OPEN, R
F
=
SHORT, R
G
= OPEN. V
S
is defined as (V
+
– V
–
). V
OUTCM
is defined as (V
OUT1
+ V
OUT2
)/2. V
OUTDIFF
is defined as (V
OUT1
– V
OUT2
). See Figure 1.
PARAMETER
Full Power Bandwidth (Note 11)
Capacitive Load Drive, 20% Overshoot
Differential Slew Rate
10kHz Distortion
HD2
HD3
100kHz Distortion
HD2
HD3
1MHz Distortion
HD2
HD3
t
S
Settling Time to a 4V Input Step
CONDITIONS
V
OUTDIFF
= 8V
P-P
No Series Output Resistors
OUT1 Rising (OUT2 Falling)
OUT1 Falling (OUT2 Rising)
V
S
= 5V, V
OUTDIFF
= 4V
P-P
, R
L
= 2kΩ
2nd Harmonic
3rd Harmonic
V
S
= 5V, V
OUTDIFF
= 4V
P-P
, R
L
= 2kΩ
2nd Harmonic
3rd Harmonic
V
S
= 5V, V
OUTDIFF
= 4V
P-P
, R
L
= 2kΩ
2nd Harmonic
3rd Harmonic
0.1%
0.01%
0.0015% (±1LSB, 16-Bit, Falling Edge)
+IN1 to V
–
and V
+
V
SHDN
= 0V to 5V
V
SHDN
= 5V to 0V
MIN
TYP
1.6
56
48
41
–115
–115
–102
–97
–86
–75
200
240
350
200
400
400
MAX
SYMBOL
FPBW
C
L
SR
UNITS
MHz
pF
V/μs
V/μs
dBc
dBc
dBc
dBc
dBc
dBc
ns
ns
ns
ns
ns
ns
t
OVDR
t
ON
t
OFF
Overdrive Recovery Time
Turn-On Time
Turn-Off Time
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Inputs are protected by back-to-back diodes and diodes to each
supply. If the inputs are taken beyond the supplies or the differential input
voltage exceeds 0.7V, the input current must be limited to less than 20mA.
Note 3:
A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted indefinitely.
Note 4:
The LT6350C/LT6350I are guaranteed functional over the
temperature range of –40°C to 85°C. The LT6350H is guaranteed
functional over the temperature range of –40°C to 125°C.
Note 5:
The LT6350C is guaranteed to meet specified performance from
0°C to 70°C. The LT6350C is designed, characterized and expected to
meet specified performance from –40°C to 85°C, but is not tested or
QA sampled at these temperatures. The LT6350I is guaranteed to meet
specified performance from –40°C to 85°C. The LT6350H is guaranteed to
meet specified performance from –40°C to 125°C.
Note 6:
V
OS2
is measured as the total output common mode voltage offset
(error between output common mode and voltage at V2). V
OS2
includes
the combined effects of op amp 2’s voltage offset, I
B
, I
OS
and mismatch
between on-chip resistors and the 499Ω external resistor, R1 (See Figure 1).
Note 7:
Supply voltage range is guaranteed by the power supply rejection
ratio test.
Note 8:
Output balance is calculated from gain error and gain as:
BAL
=
GAIN
GAIN
ERR
Note 9:
DC linearity is measured by measuring the differential output for
each input in the set V
+IN1
= 0.5V, 2.5V, 4.5V, and calculating the maximum
deviation from the least squares best fit straight line generated from the
three data points.
Note 10:
Output voltage swings are measured between the output and
power supply rails.
Note 11:
Full- power bandwidth is calculated from the slew rate.
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
