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TMS320UC5409
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
D
Advanced Multibus Architecture With Three
D
D
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
40-Bit Arithmetic Logic Unit (ALU),
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Data Bus With a Bus-Holder Feature
Extended Addressing Mode for 8M
×
16-Bit
Maximum Addressable External Program
Space
16K x 16-Bit On-Chip ROM
32K x 16-Bit Dual-Access On-Chip RAM
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
Block-Memory-Move Instructions for Better
Program and Data Management
Instructions With a 32-Bit Long Word
Operand
Instructions With Two- or Three-Operand
Reads
D
Arithmetic Instructions With Parallel Store
D
D
D
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
On-Chip Peripherals
− Software-Programmable Wait-State
Generator and Programmable Bank
Switching
− On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
− Three Multichannel Buffered Serial Ports
(McBSPs)
− Enhanced 8-Bit Parallel Host-Port
Interface With 16-Bit Data/Addressing
− One 16-Bit Timer
− Six-Channel Direct Memory Access
(DMA) Controller
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1
†
(JTAG) Boundary Scan
Logic
12.5-ns Single-Cycle Fixed-Point
Instruction Execution Time (80 MIPS)
1.8-V Core Power Supply
1.8-V to 3.6-V I/O Power Supply Enables
Operation With a SIngle 1.8-V Supply or
With Dual Power Supplies
Available in a 144-Pin Plastic Thin Quad
Flatpack (TQFP) (PGE Suffix) and a 144-Pin
Ball Grid Array (BGA) (GGU Suffix)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright
2008, Texas Instruments Incorporated
POST OFFICE BOX 1443
•
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1
ADVANCE INFORMATION
TMS320UC5409
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
TMS320UC5409 PGE package (top view) . . . . . . . . . . . . . . 5
TMS320UC5409 GGU package (bottom view) . . . . . . . . . . . 6
pin assignments on TMS320UC5409GGU . . . . . . . . . . . . . . 7
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
on-chip ROM with bootloader . . . . . . . . . . . . . . . . . . . . 12
on-chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
extended program memory . . . . . . . . . . . . . . . . . . . . . . 15
on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
software-programmable wait-state generator . . . . . . . 16
programmable bank-switching wait states . . . . . . . . . 18
parallel I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
enhanced 8-bit host-port interface (HPI8/16) . . . . . . . 19
HPI nonmultiplexed mode . . . . . . . . . . . . . . . . . . . . . . . 20
multichannel buffered serial ports . . . . . . . . . . . . . . . . 21
sample rate generator external clock options . . . . . . . 23
hardware timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
memory-mapped registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
McBSP control registers and subaddresses . . . . . . . . 35
DMA subbank addressed registers . . . . . . . . . . . . . . . 35
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device and development-support tool nomenclature . .
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions . . . . . . . . . . . . . . . .
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
internal oscillator with external crystal . . . . . . . . . . . . . .
divide-by-two clock option . . . . . . . . . . . . . . . . . . . . . . . .
multiply-by-N clock option . . . . . . . . . . . . . . . . . . . . . . . .
memory and parallel I/O interface timing . . . . . . . . . . . .
ready timing for externally generated wait states . . . . .
HOLD and HOLDA timings . . . . . . . . . . . . . . . . . . . . . . .
reset, BIO, interrupt, and MP/MC timings . . . . . . . . . . .
instruction acquisition (IAQ), interrupt acknowledge
(IACK), external flag (XF), and
TOUT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing . . . . . . . . . . . . .
HPI8 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HPI16 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
package thermal resistance characteristics . . . . .
packaging information . . . . . . . . . . . . . . . . . . . . . . .
37
39
40
41
41
42
43
44
45
46
52
56
57
59
61
68
72
76
76
76
ADVANCE INFORMATION
2
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
TMS320UC5409
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS101D device-specific data
sheet to make it an SPRS101E revision.
Scope:
This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date with the following changes.
PAGE(S)
NO.
11
Terminal Functions table:
− Updated DESCRIPTION of TRST
− Added footnote about TRST
ADDITIONS/CHANGES/DELETIONS
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251−1443
3
ADVANCE INFORMATION
TMS320UC5409
FIXED POINT DIGITAL SIGNAL PROCESSOR
SPRS101E − APRIL 1999 − REVISED OCTOBER 2008
description
The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5409 unless
otherwise specified) is ideal for low-power, high-performance applications. This processor offers very low power
consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage
enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems.
This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V
systems.
The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the UC5409 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
For detailed information on the architecture of the C5000 family of DSPs, see the
TMS320C54xE DSP
Functional Overview
(literature number SPRU307).
ADVANCE INFORMATION
4
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•
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DSP 与 ARM 处理器
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