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HD74HC161RP-EL

产品描述Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, FP-16DN
产品类别逻辑    逻辑   
文件大小89KB,共16页
制造商Hitachi (Renesas )
官网地址http://www.renesas.com/eng/
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HD74HC161RP-EL概述

Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16, FP-16DN

HD74HC161RP-EL规格参数

参数名称属性值
厂商名称Hitachi (Renesas )
零件包装代码SOIC
包装说明SOP,
针数16
Reach Compliance Codeunknown
计数方向UP
系列HC/UH
JESD-30 代码R-PDSO-G16
长度9.9 mm
负载/预设输入YES
逻辑集成电路类型BINARY COUNTER
工作模式SYNCHRONOUS
位数4
功能数量1
端子数量16
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE
传播延迟(tpd)200 ns
认证状态Not Qualified
座面最大高度1.75 mm
最大供电电压 (Vsup)6 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)4.5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
触发器类型POSITIVE EDGE
宽度3.95 mm
Base Number Matches1

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HD74HC160/HD74HC161/
HD74HC162/HD74HC163
Synchronous Decade Counter (Direct Clear)
Synchronous 4-bit Binary Counter (Direct Clear)
Synchronous Decade Counter (Synchronous Clear)
Synchronous 4-bit Binary Counter (Synchronous Clear)
Description
The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the
HD74HC163 are 4 bit binary counters All flip-flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform.
These counters may be preset using the load input. Presetting of all four flip-flops is synchronous to thte
rising edge of clock. When load is held low counting is disabled and the data on the A, B, C, and D inputs
is loaded into the counter on the rising edge of clock. If the load input is taken high before the positive
edge of clock the count operation will be unaffected.
All of these counters may be cleared by utilizing the clear input. The clear function on the HD74HC162
and HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive
edge of clock while the clear input is held low.
The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the
counter is cleared immediately regardless of the clock.
Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy
cascading of counters. Both enable inputs must be high to count. The Enable T input also enables the
Ripple Carry output. When enabled, the Ripple Carry outputs a positive pulse when the counter overflows.
This pulse is approximately equal in duration to the high level portion of the Q
A
outputs. The Ripple Carry
output is fed to successive cascaded stages to facilitate easy implementation of N-bit counters.
Features
High Speed Operation: t
pd
(Clock to Q) = 18 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 µA max

 
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