HD74ALVCH16836
20-bit Universal Bus Driver with 3-state Outputs
ADE-205-213 (Z)
Preliminary
1st. Edition
January 1998
Description
This 20-bit universal bus driver is designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (O
E)
input. The device operates in the
transparent mode when the latch enable (LE) input is low. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If
LE
is high, the A data is stored in the latch flip flop on the low to high
transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating inputs at a valid logic level.
Features
•
V
CC
= 2.3 V to 3.6 V
•
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
•
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25°C)
•
High output current ±24 mA (@V
CC
= 3.0 V)
•
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16836
Function Table
Inputs
OE
H
L
L
L
L
L
L
LE
X
L
L
H
H
H
H
CLK
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
Z
L
H
L
H
Y
0
Y
0
*1
*2
Output Y
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑
: Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established, provided that
CLK is high before
LE
goes low.
2. Output level before the indicated steady state input conditions were established.
2
HD74ALVCH16836
Pin Arrangement
OE
1
Y1 2
Y2 3
GND 4
Y3 5
Y4 6
V
CC
7
Y5 8
Y6 9
Y7 10
GND 11
Y8 12
Y9 13
Y10 14
Y11 15
Y12 16
Y13 17
GND 18
Y14 19
Y15 20
Y16 21
V
CC
22
Y17 23
Y18 24
GND 25
Y19 26
Y20 27
NC 28
56 CLK
55 A1
54 A2
53 GND
52 A3
51 A4
50 V
CC
49 A5
48 A6
47 A7
46 GND
45 A8
44 A9
43 A10
42 A11
41 A12
40 A13
39 GND
38 A14
37 A15
36 A16
35 V
CC
34 A17
33 A18
32 GND
31 A19
30 A20
29
LE
(Top view)
3
HD74ALVCH16836
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1
Output voltage
*1, 2
Input clamp current
Output clamp current
Continuous output current
V
CC
, GND current / pin
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature
Notes:
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or I
GND
P
T
Tstg
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to V
CC
+0.5
–50
±50
±50
±100
1
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
W
°C
TSSOP
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
High level output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.3
0
0
—
—
—
Low level output current
I
OL
—
—
—
Input transition rise or fall rate
Operating temperature
∆t
/
∆v
Ta
0
–40
Max
3.6
V
CC
V
CC
–12
–12
–24
12
12
24
10
85
ns / V
°C
mA
Unit
V
V
V
mA
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
V
CC
= 2.3 V
V
CC
= 2.7 V
V
CC
= 3.0 V
Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
4
HD74ALVCH16836
Logic Diagram
OE
CLK
LE
A1
1
56
29
55
1D
C1
CLK
2
Y1
To nineteen other channels
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
