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HYMD512G726BFP4N-D43: 产品描述DDR DRAM Module, 128MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184; 产品类别存储存储; 文件大小436KB，共20页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/; 标准

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HYMD512G726BFP4N-D43概述

DDR DRAM Module, 128MX72, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184

HYMD512G726BFP4N-D43规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	DIMM, DIMM184
针数	184
Reach Compliance Code	unknown
ECCN代码	EAR99
访问模式	SINGLE BANK PAGE BURST
最长访问时间	0.7 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	200 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N184
JESD-609代码	e1
内存密度	9663676416 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	72
功能数量	1
端口数量	1
端子数量	184
字数	134217728 words
字数代码	128000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128MX72
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM184
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）	260
电源	2.6 V
认证状态	Not Qualified
刷新周期	8192
自我刷新	YES
最大待机电流	0.63 A
最大压摆率	10.37 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.5 V
标称供电电压 (Vsup)	2.6 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	20
Base Number Matches	1

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184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (FBGA)

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 60 ball

FBGA package on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based Registered DIMM series provide a

high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange

and addition.

FEATURES

•

JEDEC Standard 184-pin dual in-line memory module

(DIMM)

One rank 128M x 72, 64M x 72 organization

Error Check Correction (ECC) Capability

2.6V

0.1V VDD and VDDQ Power supply for

DDR400 and 2.5V

0.2V for DDR333

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

166/200MHz

DLL aligns DQ and DQS transition with CK transition

Programmable CAS Latency: DDR333(2.5 clock),

DDR400(3 clock)

•

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

Edge-aligned DQS with data outs and Center-aligned

DQS with data inputs

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

Serial Presence Detect (SPD) with EEPROM

Built with 512Mb DDR SDRAMs in 60 ball FBGA pack-

ages

Lead-free product listed for each configuration

(RoHS compliant)

ADDRESS TABLE

Organization

512MB

1GB

64M x 72

128M x 72

Ranks

SDRAMs

64Mb x 8

128Mb x 4

# of

DRAMs

# of row/bank/column Address

13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)

13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12)

Refresh

Method

8K / 64ms

PREFORMANCE

Part-Number Suffix

Speed Bin

CL - tRCD- tRP

CL=3

Max Clock

Frequency

CL=2.5

CL=2

-D43

DDR400B

3-3-3

200

166

133

-J

DDR333

2.5-3-3

166

133

Unit

MHz

Note:

1. 2.6V

0.1V VDD and VDDQ Power supply for DDR400 and 2.5V

0.2V for DDR333

Rev. 1.1 /May. 2005

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

HYMD512G726BFP4N-D43

HYMD512G726BFP4N-D43概述

HYMD512G726BFP4N-D43规格参数

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