78A207
MFR1 Receiver
April 2000
DESCRIPTION
The 78A207 is a single-chip, Multi-Frequency (MF)
receiver that can detect all 15 tone-pairs, including
ST and KP framing tones. This receiver is intended
for use in equal access applications and thus meets
both Bell and CCITT R1 central office register
signaling specifications.
The 78A207 employs state-of-the-art switched
capacitor filters in CMOS technology. The receiver
consists of a bank of channel-separation bandpass
filters followed by zero-crossing detectors and
frequency-measurement
bandpass
filters,
an
amplitude check circuit, a timer and decoder circuit,
and a clock generator. The device does not attempt
to identify strings of digits by the KP (key pulse) and
ST (stop) tone pairs.
No anti-alias filtering is needed if the input signal is
band-limited to 26 KHz. The only external
component required is an inexpensive television
“color burst” 3.58 MHz crystal.
The outputs interface directly with standard CMOS
or TTL circuitry and are three-state enabled to
facilitate bus-oriented architecture.
FEATURES
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Meets Bell and CCITT R1 specifications
20-pin plastic DIP
Single low-tolerance 5V supply
Detects all 15 tone-pairs including ST and KP
Long KP capability
Built-in amplitude discrimination
Excellent noise tolerance
Outputs in either “n of 6” or hexadecimal code
Three-state outputs, CMOS-compatible and
TTL-compatible
BLOCK DIAGRAM
700
VIN
900
700
THRESHOLD
DETECTOR
QUAL
LOGIC
R
Q
S
CSTR
DV
900
R
1100
1100
S
Q
DE
1300
1300
LKP
1500
1500
HEX
QUAL
1700
PRE-FILTER
X1
ZERO
CROSSING
DETECTORS
1700
BANDPASS
FILTER
D5
D4
D3
D2
X2
CLOCK
GENERATOR
CHIP CLOCKS
D1
D0
XOUT
VOLTAGE DIVIDER
VOLTAGE
REF
TONE DETECTOR
EN
AGN
VDD
DGND
78A207
MFR1 Receiver
FUNCTIONAL DESCRIPTION
VIN
This pin accepts the analog input. It is internally
biased to half the supply and is capacitively coupled
to the channel separation filters. The input may be
DC coupled as long as it does not exceed VDD or
drop below GND. Equivalent input circuit is shown
below in Figure 1.
CRYSTAL OSCILLATOR
The 78A207 contains an on-board inverter with
sufficient gain to provide oscillation when connected
to a low cost television “color-burst” crystal. The on-
chip clock signals are generated from the oscillator.
The crystal is connected between X1 and X2.
XOUT is a 3.58 MHz square wave capable of driving
other circuits as long as the capacitive load does not
exceed 50 pF. Other devices driven by XOUT
should use X1 as the input pin, while X2 should be
left floating.
LKP
The KP timer control: When high, the KP detect time
is increased. When low, the KP detect time is the
same as for other tones.
QUAL
Enables tone pair qualification. When low, the
threshold detector outputs are passed to the data
outputs (D0-D5) without validation in the format
selected by the HEX pin. These outputs, plus
strobes DV and DE, are updated once per 2.3 ms
frame. Note that the strobes will cycle once per
frame (even when the inputs are stable.) As always,
data changes only when both strobes are low.
CSTR
This input clears both the DV and DE strobes, and is
active low. After
CSTR
is released, the strobes will
remain low until a new detect (or error) occurs. The
output data is latched by
CSTR
and will not change
while
CSTR
is low, even in the event that a new
detect is qualified internally. (Note that improper use
of
CSTR
may result in missed detects.)
The outputs will be cleared to zero when no valid
tone pair is present.
For the “n of 6” mode, the HEX pin is pulled low, and
each output represents one of the six frequencies as
shown below:
FREQUENCY
700
900
1100
1300
1500
1700
OUTPUT PIN
D0
D1
D2
D3
D4
D5
EN
EN
The three-state enable control: When low, the D0-
D5 outputs are in the low impedance state. In an
interrupt oriented microprocessor interface,
EN
and
CSTR
will often be tied together to provide
automatic reset of the strobes when the output data
is enabled.
STROBE PINS - DV AND DE
Valid data is indicated on the DV strobe pin, and
data errors are indicated on the DE strobe pin.
Whenever a valid 2 of 6 code has been detected,
the DV strobe rises. It remains high until the code
goes away, or the
CSTR
line is activated. When an
invalid code is detected, e.g., 1 of 6, 3 of 6, etc., the
DE strobe remains high until all errors stop, a valid
tone pair is detected, or the
CSTR
line is activated.
Once cleared by
CSTR,
DE will not reactivate until a
new invalid condition is detected. The DE and DV
strobes will never be high simultaneously.
DATA OUTPUT MODES
The digital output format may be either “n of 6” or 4-
bit hexadecimal.
For “hex” mode, the HEX pin is pulled high. Outputs
D0 to D3 provide a 4-bit code identifying one of the
15 valid tone combinations according to Table1.
The outputs will be cleared to zero when no valid
tone is present.
2
FPGA/CPLD
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